📄 bit_align_machine_map.mrp
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Release 10.1.02 Map K.37 (nt)Xilinx Mapping Report File for Design 'BIT_ALIGN_MACHINE'Design Information------------------Command Line : map -ise E:/ISEworks/LVDS/xapp860/xapp860.ise -intstyle ise -p
xc5vsx50t-ff1136-1 -w -logic_opt off -ol high -t 1 -cm area -pr off -k 6 -lc off
-power off -o BIT_ALIGN_MACHINE_map.ncd BIT_ALIGN_MACHINE.ngd
BIT_ALIGN_MACHINE.pcf Target Device : xc5vsx50tTarget Package : ff1136Target Speed : -1Mapper Version : virtex5 -- $Revision: 1.46.12.2 $Mapped Date : Tue Aug 19 20:15:18 2008Design Summary--------------Number of errors: 0Number of warnings: 1Slice Logic Utilization: Number of Slice Registers: 33 out of 32,640 1% Number used as Flip Flops: 33 Number of Slice LUTs: 76 out of 32,640 1% Number used as logic: 76 out of 32,640 1% Number using O6 output only: 76Slice Logic Distribution: Number of occupied Slices: 22 out of 8,160 1% Number of LUT Flip Flop pairs used: 76 Number with an unused Flip Flop: 43 out of 76 56% Number with an unused LUT: 0 out of 76 0% Number of fully used LUT-FF pairs: 33 out of 76 43% Number of unique control sets: 3 Number of slice register sites lost to control set restrictions: 3 out of 32,640 1% A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. A control set is a unique combination of clock, reset, set, and enable signals for a registered element. The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails.IO Utilization: Number of bonded IOBs: 14 out of 480 2%Specific Feature Utilization: Number of BUFG/BUFGCTRLs: 1 out of 32 3% Number used as BUFGs: 1Peak Memory Usage: 363 MBTotal REAL time to MAP completion: 54 secs Total CPU time to MAP completion: 47 secs Table of Contents-----------------Section 1 - ErrorsSection 2 - WarningsSection 3 - InformationalSection 4 - Removed Logic SummarySection 5 - Removed LogicSection 6 - IOB PropertiesSection 7 - RPMsSection 8 - Guide ReportSection 9 - Area Group and Partition SummarySection 10 - Modular Design SummarySection 11 - Timing ReportSection 12 - Configuration String InformationSection 13 - Control Set InformationSection 14 - Utilization by HierarchySection 1 - Errors------------------Section 2 - Warnings--------------------Section 3 - Informational-------------------------INFO:MapLib:562 - No environment variables are currently set.INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
0.000 to 85.000 Celsius)INFO:Pack:1720 - Initializing voltage to 0.950 Volts. (default - Range: 0.950 to
1.050 Volts)INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).INFO:Pack:1650 - Map created a placed design.Section 4 - Removed Logic Summary---------------------------------Section 5 - Removed Logic-------------------------Section 6 - IOB Properties--------------------------+----------------------------------------------------------------------------------------------------------------------------------------+| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB || | | | | Strength | Rate | | | Delay |+----------------------------------------------------------------------------------------------------------------------------------------+| BITSLIP | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || DATA_ALIGNED | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || ICE | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || INC | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | || RST | IOB | INPUT | LVCMOS25 | | | | | || RXCLKDIV | IOB | INPUT | LVCMOS25 | | | | | || RXDATA<0> | IOB | INPUT | LVCMOS25 | | | | | || RXDATA<1> | IOB | INPUT | LVCMOS25 | | | | | || RXDATA<2> | IOB | INPUT | LVCMOS25 | | | | | || RXDATA<3> | IOB | INPUT | LVCMOS25 | | | | | || RXDATA<4> | IOB | INPUT | LVCMOS25 | | | | | || RXDATA<5> | IOB | INPUT | LVCMOS25 | | | | | || SAP | IOB | INPUT | LVCMOS25 | | | | | || USE_BITSLIP | IOB | INPUT | LVCMOS25 | | | | | |+----------------------------------------------------------------------------------------------------------------------------------------+Section 7 - RPMs----------------Section 8 - Guide Report------------------------Guide not run on this design.Section 9 - Area Group and Partition Summary--------------------------------------------Partition Implementation Status------------------------------- No Partitions were found in this design.-------------------------------Area Group Information---------------------- No area groups were found in this design.----------------------Section 10 - Modular Design Summary-----------------------------------Modular Design not used for this design.Section 11 - Timing Report--------------------------A logic-level (pre-route) timing report can be generated by using Xilinx static
timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
mapped NCD and PCF files. Please note that this timing report will be generated
using estimated delay information. For accurate numbers, please generate a
timing report with the post Place and Route NCD file.For more information about the Timing Analyzer, consult the Xilinx Timing
Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
Development System Reference Guide "TRACE" chapter.Section 12 - Configuration String Details-----------------------------------------Use the "-detail" map option to print out Configuration StringsSection 13 - Control Set Information------------------------------------Use the "-detail" map option to print out Control Set Information.Section 14 - Utilization by Hierarchy-------------------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+| Module | Partition | Slices* | Slice Reg | LUTs | LUTRAM | BRAM/FIFO | DSP48E | BUFG | BUFIO | BUFR | DCM | PLL | Full Hierarchical Name |+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+| BIT_ALIGN_MACHINE/ | | 20/28 | 12/33 | 59/76 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | 0/0 | BIT_ALIGN_MACHINE || +machine_counter | | 3/3 | 7/7 | 9/9 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | BIT_ALIGN_MACHINE/machine_counter || +machine_counter_tota | | 3/3 | 7/7 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | BIT_ALIGN_MACHINE/machine_counter_total || +tap_reserve | | 2/2 | 7/7 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | BIT_ALIGN_MACHINE/tap_reserve |+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+* Slices can be packed with basic elements from multiple hierarchies. Therefore, a slice will be counted in every hierarchical module that each of its packed basic elements belong to.** For each column, there are two numbers reported <A>/<B>. <A> is the number of elements that belong to that specific hierarchical module. <B> is the total number of elements from that hierarchical module and any lower level hierarchical modules below.*** The LUTRAM column counts all LUTs used as memory including RAM, ROM, and shift registers.⌨️ 快捷键说明
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