lvds_tx_rx_merge.pcf

FPGA之间的LVDS传输

        = BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP"
        PINNAME WRCLKU;
PIN
        uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_pins<184>
        = BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP"
        PINNAME RDCLKL;
PIN
        uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_pins<185>
        = BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP"
        PINNAME RDCLKU;
PIN
        uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_pins<188>
        = BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP"
        PINNAME RDRCLKL;
PIN
        uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_pins<189>
        = BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP"
        PINNAME RDRCLKU;
TIMEGRP CLK_USR = BEL "uut_rx/DATA_RX_FIFO_63" BEL "uut_rx/DATA_RX_FIFO_62"
        BEL "uut_rx/DATA_RX_FIFO_61" BEL "uut_rx/DATA_RX_FIFO_60" BEL
        "uut_rx/DATA_RX_FIFO_59" BEL "uut_rx/DATA_RX_FIFO_58" BEL
        "uut_rx/DATA_RX_FIFO_57" BEL "uut_rx/DATA_RX_FIFO_56" BEL
        "uut_rx/DATA_RX_FIFO_55" BEL "uut_rx/DATA_RX_FIFO_54" BEL
        "uut_rx/DATA_RX_FIFO_53" BEL "uut_rx/DATA_RX_FIFO_52" BEL
        "uut_rx/DATA_RX_FIFO_51" BEL "uut_rx/DATA_RX_FIFO_50" BEL
        "uut_rx/DATA_RX_FIFO_49" BEL "uut_rx/DATA_RX_FIFO_48" BEL
        "uut_rx/DATA_RX_FIFO_47" BEL "uut_rx/DATA_RX_FIFO_46" BEL
        "uut_rx/DATA_RX_FIFO_45" BEL "uut_rx/DATA_RX_FIFO_44" BEL
        "uut_rx/DATA_RX_FIFO_43" BEL "uut_rx/DATA_RX_FIFO_42" BEL
        "uut_rx/DATA_RX_FIFO_41" BEL "uut_rx/DATA_RX_FIFO_40" BEL
        "uut_rx/DATA_RX_FIFO_39" BEL "uut_rx/DATA_RX_FIFO_38" BEL
        "uut_rx/DATA_RX_FIFO_37" BEL "uut_rx/DATA_RX_FIFO_36" BEL
        "uut_rx/DATA_RX_FIFO_35" BEL "uut_rx/DATA_RX_FIFO_34" BEL
        "uut_rx/DATA_RX_FIFO_33" BEL "uut_rx/DATA_RX_FIFO_32" BEL
        "uut_rx/DATA_RX_FIFO_31" BEL "uut_rx/DATA_RX_FIFO_30" BEL
        "uut_rx/DATA_RX_FIFO_29" BEL "uut_rx/DATA_RX_FIFO_28" BEL
        "uut_rx/DATA_RX_FIFO_27" BEL "uut_rx/DATA_RX_FIFO_26" BEL
        "uut_rx/DATA_RX_FIFO_25" BEL "uut_rx/DATA_RX_FIFO_24" BEL
        "uut_rx/DATA_RX_FIFO_23" BEL "uut_rx/DATA_RX_FIFO_22" BEL
        "uut_rx/DATA_RX_FIFO_21" BEL "uut_rx/DATA_RX_FIFO_20" BEL
        "uut_rx/DATA_RX_FIFO_19" BEL "uut_rx/DATA_RX_FIFO_18" BEL
        "uut_rx/DATA_RX_FIFO_17" BEL "uut_rx/DATA_RX_FIFO_16" BEL
        "uut_rx/DATA_RX_FIFO_15" BEL "uut_rx/DATA_RX_FIFO_14" BEL
        "uut_rx/DATA_RX_FIFO_13" BEL "uut_rx/DATA_RX_FIFO_12" BEL
        "uut_rx/DATA_RX_FIFO_11" BEL "uut_rx/DATA_RX_FIFO_10" BEL
        "uut_rx/DATA_RX_FIFO_9" BEL "uut_rx/DATA_RX_FIFO_8" BEL
        "uut_rx/DATA_RX_FIFO_7" BEL "uut_rx/DATA_RX_FIFO_6" BEL
        "uut_rx/DATA_RX_FIFO_5" BEL "uut_rx/DATA_RX_FIFO_4" BEL
        "uut_rx/DATA_RX_FIFO_3" BEL "uut_rx/DATA_RX_FIFO_2" BEL
        "uut_rx/DATA_RX_FIFO_1" BEL "uut_rx/DATA_RX_FIFO_0" BEL
        "uut_tx/DATA_TX_FIFO_RDY" BEL "uut_rx/rd_en" BEL
        "uut_rx/Mshreg_DATA_RX_FIFO_VLD" BEL "uut_rx/DATA_RX_FIFO_VLD" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/rstblk/wr_rst_asreg_d2" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/rstblk/wr_rst_asreg" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/rstblk/wr_rst_asreg_d1" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/rstblk/wr_rst_reg_1" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/rstblk/wr_rst_reg_0" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/wr_rst_d1" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_fb_i" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_5" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_4" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_3" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_2" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_1" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/rd_pntr_bin_0" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_5" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_4" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_3" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_2" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_1" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_d1_0" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_5" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_4" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_3" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_2" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_1" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_asreg_0" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_5" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_4" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_3" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_2" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_1" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_0" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gl0.wr/wpntr/count_4" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gl0.wr/wpntr/count_3" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gl0.wr/wpntr/count_5" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gl0.wr/wpntr/count_1" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gl0.wr/wpntr/count_0" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gl0.wr/wpntr/count_2" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_2" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_0" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_1" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_5" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_3" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gl0.wr/wpntr/count_d1_4" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_2" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_0" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_1" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_5" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_3" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gl0.wr/wpntr/count_d2_4" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_5" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_4" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_3" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_2" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_1" BEL
        "uut_tx/U_FIFO/BU2/U0/grf.rf/gl0.wr/wpntr/count_d3_0" PIN
        "uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_pins<252>"
        PIN
        "uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_pins<253>"
        PIN
        "uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_pins<252>"
        PIN
        "uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_pins<253>"
        BEL "uut_rx/U_FIFO/BU2/U0/grf.rf/rstblk/rd_rst_asreg_d2" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/rstblk/rd_rst_asreg_d1" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/rstblk/rd_rst_asreg" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/rstblk/rd_rst_reg_2" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/rstblk/rd_rst_reg_1" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/rstblk/rd_rst_reg_0" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_fb_i" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_almost_empty_i" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_5" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_4" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_3" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_2" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_1" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/wr_pntr_bin_0" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_5" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_4" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_3" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_2" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_1" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_d1_0" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_5" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_4" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_3" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_2" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_1" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg_0" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_5" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_4" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_3" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_2" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_1" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/rd_pntr_gc_0" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.rd/rpntr/count_4" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.rd/rpntr/count_3" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.rd/rpntr/count_5" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.rd/rpntr/count_1" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.rd/rpntr/count_0" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.rd/rpntr/count_2" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_2" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_0" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_1" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_5" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_3" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.rd/rpntr/count_d1_4" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.rd/rpntr/count_d2_5" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.rd/rpntr/count_d2_4" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.rd/rpntr/count_d2_3" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.rd/rpntr/count_d2_2" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.rd/rpntr/count_d2_1" BEL
        "uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.rd/rpntr/count_d2_0" PIN
        "uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_pins<184>"
        PIN
        "uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_pins<185>"
        PIN
        "uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_pins<188>"
        PIN
        "uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_pins<189>"
        PIN
        "uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_pins<184>"
        PIN
        "uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_pins<185>"
        PIN
        "uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_pins<188>"
        PIN
        "uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_pins<189>"
        PIN
        "uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_pins<184>"
        PIN
        "uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_pins<185>"
        PIN
        "uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_pins<188>"
        PIN
        "uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_pins<189>"
        PIN
        "uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_pins<184>"
        PIN
        "uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_pins<185>"
        PIN
        "uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_pins<188>"
        PIN
        "uut_rx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_pins<189>";
TS_TXCLKDIV = PERIOD TIMEGRP "TXCLKDIV" 6 ns HIGH 50%;
TS_CLK_USR = PERIOD TIMEGRP "CLK_USR" 6 ns HIGH 50%;
SCHEMATIC END;