lvds_bist_top.pcf

来自「FPGA之间的LVDS传输」· PCF 代码 · 共 965 行 · 第 1/5 页

//! **************************************************************************
// Written by: Map K.37 on Sun Jan 11 23:08:23 2009
//! **************************************************************************

SCHEMATIC START;
COMP "DATA_RX_N<10>" LOCATE = SITE "L19" LEVEL 1;
COMP "DATA_RX_N<11>" LOCATE = SITE "J25" LEVEL 1;
COMP "DATA_RX_N<12>" LOCATE = SITE "G17" LEVEL 1;
COMP "DATA_RX_N<13>" LOCATE = SITE "L25" LEVEL 1;
COMP "DATA_RX_N<14>" LOCATE = SITE "K19" LEVEL 1;
COMP "DATA_RX_N<15>" LOCATE = SITE "M24" LEVEL 1;
COMP "DATA_RX_N<16>" LOCATE = SITE "H18" LEVEL 1;
COMP "DATA_RX_P<10>" LOCATE = SITE "L20" LEVEL 1;
COMP "DATA_RX_P<11>" LOCATE = SITE "K25" LEVEL 1;
COMP "DATA_RX_P<12>" LOCATE = SITE "G18" LEVEL 1;
COMP "DATA_RX_P<13>" LOCATE = SITE "K24" LEVEL 1;
COMP "DATA_RX_P<14>" LOCATE = SITE "K18" LEVEL 1;
COMP "DATA_RX_P<15>" LOCATE = SITE "L24" LEVEL 1;
COMP "DATA_RX_P<16>" LOCATE = SITE "J18" LEVEL 1;
COMP "DATA_TX_N<10>" LOCATE = SITE "M33" LEVEL 1;
COMP "DATA_TX_N<11>" LOCATE = SITE "L31" LEVEL 1;
COMP "DATA_TX_N<12>" LOCATE = SITE "G34" LEVEL 1;
COMP "DATA_TX_N<13>" LOCATE = SITE "J33" LEVEL 1;
COMP "DATA_TX_N<14>" LOCATE = SITE "P31" LEVEL 1;
COMP "DATA_TX_N<15>" LOCATE = SITE "M31" LEVEL 1;
COMP "DATA_TX_N<16>" LOCATE = SITE "F32" LEVEL 1;
COMP "DATA_TX_P<10>" LOCATE = SITE "M34" LEVEL 1;
COMP "DATA_TX_P<11>" LOCATE = SITE "L32" LEVEL 1;
COMP "DATA_TX_P<12>" LOCATE = SITE "H34" LEVEL 1;
COMP "DATA_TX_P<13>" LOCATE = SITE "K33" LEVEL 1;
COMP "DATA_TX_P<14>" LOCATE = SITE "N31" LEVEL 1;
COMP "DATA_TX_P<15>" LOCATE = SITE "M32" LEVEL 1;
COMP "DATA_TX_P<16>" LOCATE = SITE "F31" LEVEL 1;
COMP "CLK_50M" LOCATE = SITE "AM16" LEVEL 1;
COMP "DATA_TX_N<0>" LOCATE = SITE "J31" LEVEL 1;
COMP "DATA_TX_N<1>" LOCATE = SITE "G31" LEVEL 1;
COMP "DATA_TX_N<2>" LOCATE = SITE "H33" LEVEL 1;
COMP "DATA_TX_N<3>" LOCATE = SITE "J32" LEVEL 1;
COMP "DATA_TX_N<4>" LOCATE = SITE "R32" LEVEL 1;
COMP "DATA_TX_N<5>" LOCATE = SITE "P32" LEVEL 1;
COMP "DATA_TX_N<6>" LOCATE = SITE "U32" LEVEL 1;
COMP "DATA_TX_N<7>" LOCATE = SITE "N34" LEVEL 1;
COMP "DATA_TX_P<0>" LOCATE = SITE "H31" LEVEL 1;
COMP "DATA_TX_N<8>" LOCATE = SITE "E33" LEVEL 1;
COMP "DATA_TX_P<1>" LOCATE = SITE "G32" LEVEL 1;
COMP "DATA_TX_N<9>" LOCATE = SITE "T31" LEVEL 1;
COMP "DATA_TX_P<2>" LOCATE = SITE "G33" LEVEL 1;
COMP "DATA_TX_P<3>" LOCATE = SITE "K32" LEVEL 1;
COMP "DATA_TX_P<4>" LOCATE = SITE "R33" LEVEL 1;
COMP "DATA_TX_P<5>" LOCATE = SITE "P33" LEVEL 1;
COMP "DATA_TX_P<6>" LOCATE = SITE "T32" LEVEL 1;
COMP "DATA_TX_P<7>" LOCATE = SITE "N33" LEVEL 1;
COMP "DATA_TX_P<8>" LOCATE = SITE "E32" LEVEL 1;
COMP "DATA_TX_P<9>" LOCATE = SITE "U31" LEVEL 1;
COMP "DATA_RX_N<0>" LOCATE = SITE "H28" LEVEL 1;
COMP "DATA_RX_N<1>" LOCATE = SITE "H16" LEVEL 1;
COMP "DATA_RX_N<2>" LOCATE = SITE "H30" LEVEL 1;
COMP "DATA_RX_N<3>" LOCATE = SITE "F17" LEVEL 1;
COMP "DATA_RX_N<4>" LOCATE = SITE "F29" LEVEL 1;
COMP "DATA_RX_N<5>" LOCATE = SITE "N18" LEVEL 1;
COMP "DATA_RX_N<6>" LOCATE = SITE "F27" LEVEL 1;
COMP "DATA_RX_N<7>" LOCATE = SITE "N19" LEVEL 1;
COMP "DATA_RX_P<0>" LOCATE = SITE "G28" LEVEL 1;
COMP "DATA_RX_N<8>" LOCATE = SITE "J27" LEVEL 1;
COMP "DATA_RX_P<1>" LOCATE = SITE "G16" LEVEL 1;
COMP "DATA_RX_N<9>" LOCATE = SITE "J26" LEVEL 1;
COMP "DATA_RX_P<2>" LOCATE = SITE "H29" LEVEL 1;
COMP "DATA_RX_P<3>" LOCATE = SITE "F16" LEVEL 1;
COMP "DATA_RX_P<4>" LOCATE = SITE "G29" LEVEL 1;
COMP "DATA_RX_P<5>" LOCATE = SITE "M18" LEVEL 1;
COMP "DATA_RX_P<6>" LOCATE = SITE "G27" LEVEL 1;
COMP "DATA_RX_P<7>" LOCATE = SITE "M19" LEVEL 1;
COMP "DATA_RX_P<8>" LOCATE = SITE "J28" LEVEL 1;
COMP "DATA_RX_P<9>" LOCATE = SITE "H26" LEVEL 1;
COMP "CLOCK_RX_N" LOCATE = SITE "L26" LEVEL 1;
COMP "CLOCK_RX_P" LOCATE = SITE "K27" LEVEL 1;
COMP "TRAINING_DONE_RX" LOCATE = SITE "V36" LEVEL 1;
COMP "TRAINING_DONE_TX" LOCATE = SITE "U36" LEVEL 1;
COMP "RESET_N" LOCATE = SITE "AM17" LEVEL 1;
COMP "CLOCK_TX_N" LOCATE = SITE "F34" LEVEL 1;
COMP "CLOCK_TX_P" LOCATE = SITE "E34" LEVEL 1;
PIN u_lvds/uut_tx/OSERDES_TX_DATA_00_pins<1> = BEL
        "u_lvds/uut_tx/OSERDES_TX_DATA_00" PINNAME CLKDIV;
PIN u_lvds/uut_tx/OSERDES_TX_DATA_01_pins<1> = BEL
        "u_lvds/uut_tx/OSERDES_TX_DATA_01" PINNAME CLKDIV;
PIN u_lvds/uut_tx/OSERDES_TX_DATA_02_pins<1> = BEL
        "u_lvds/uut_tx/OSERDES_TX_DATA_02" PINNAME CLKDIV;
PIN u_lvds/uut_tx/OSERDES_TX_DATA_03_pins<1> = BEL
        "u_lvds/uut_tx/OSERDES_TX_DATA_03" PINNAME CLKDIV;
PIN u_lvds/uut_tx/OSERDES_TX_DATA_04_pins<1> = BEL
        "u_lvds/uut_tx/OSERDES_TX_DATA_04" PINNAME CLKDIV;
PIN u_lvds/uut_tx/OSERDES_TX_DATA_05_pins<1> = BEL
        "u_lvds/uut_tx/OSERDES_TX_DATA_05" PINNAME CLKDIV;
PIN u_lvds/uut_tx/OSERDES_TX_DATA_06_pins<1> = BEL
        "u_lvds/uut_tx/OSERDES_TX_DATA_06" PINNAME CLKDIV;
PIN u_lvds/uut_tx/OSERDES_TX_DATA_07_pins<1> = BEL
        "u_lvds/uut_tx/OSERDES_TX_DATA_07" PINNAME CLKDIV;
PIN u_lvds/uut_tx/OSERDES_TX_DATA_08_pins<1> = BEL
        "u_lvds/uut_tx/OSERDES_TX_DATA_08" PINNAME CLKDIV;
PIN u_lvds/uut_tx/OSERDES_TX_DATA_09_pins<1> = BEL
        "u_lvds/uut_tx/OSERDES_TX_DATA_09" PINNAME CLKDIV;
PIN u_lvds/uut_tx/OSERDES_TX_DATA_10_pins<1> = BEL
        "u_lvds/uut_tx/OSERDES_TX_DATA_10" PINNAME CLKDIV;
PIN u_lvds/uut_tx/OSERDES_TX_DATA_11_pins<1> = BEL
        "u_lvds/uut_tx/OSERDES_TX_DATA_11" PINNAME CLKDIV;
PIN u_lvds/uut_tx/OSERDES_TX_DATA_12_pins<1> = BEL
        "u_lvds/uut_tx/OSERDES_TX_DATA_12" PINNAME CLKDIV;
PIN u_lvds/uut_tx/OSERDES_TX_DATA_13_pins<1> = BEL
        "u_lvds/uut_tx/OSERDES_TX_DATA_13" PINNAME CLKDIV;
PIN u_lvds/uut_tx/OSERDES_TX_DATA_14_pins<1> = BEL
        "u_lvds/uut_tx/OSERDES_TX_DATA_14" PINNAME CLKDIV;
PIN u_lvds/uut_tx/OSERDES_TX_DATA_15_pins<1> = BEL
        "u_lvds/uut_tx/OSERDES_TX_DATA_15" PINNAME CLKDIV;
PIN u_lvds/uut_tx/OSERDES_TX_Cntl_pins<1> = BEL
        "u_lvds/uut_tx/OSERDES_TX_Cntl" PINNAME CLKDIV;
PIN
        u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP_pins<72>
        = BEL
        "u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP"
        PINNAME CLKBL;
PIN
        u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP_pins<73>
        = BEL
        "u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP"
        PINNAME CLKBU;
PIN
        u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP_pins<228>
        = BEL
        "u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP"
        PINNAME REGCLKBL;
PIN
        u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP_pins<229>
        = BEL
        "u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP"
        PINNAME REGCLKBU;
PIN
        u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP_pins<72>
        = BEL
        "u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP"
        PINNAME CLKBL;
PIN
        u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP_pins<73>
        = BEL
        "u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP"
        PINNAME CLKBU;
PIN
        u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP_pins<228>
        = BEL
        "u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP"
        PINNAME REGCLKBL;
PIN
        u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP_pins<229>
        = BEL
        "u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/mem/gbm.gbmg.gbmga.ngecc.bmg/blk_mem_generator/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.SINGLE_PRIM36.TDP"
        PINNAME REGCLKBU;
TIMEGRP CLK100 = BEL "RESET_r_1" BEL "RESET_r_2" BEL "RESET_r_3" BEL
        "RESET_r_4" BEL "RESET_r_5" BEL "RESET_r_6" BEL "RESET_r_7" BEL
        "RESET_r_8" BEL "RESET_r_9" BEL "u_lvds/uut_tx/FIFO_DATA_VALID" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_1" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_2" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_5" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_6" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_9" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_10" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_13" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_14" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_17" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_18" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_21" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_22" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_25" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_26" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_29" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_30" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_33" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_34" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_37" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_38" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_41" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_42" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_45" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_46" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_49" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_50" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_53" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_54" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_57" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_58" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_61" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_62" BEL
        "u_lvds/uut_tx/DATA_TO_OSERDES_REG_65" PIN
        "u_lvds/uut_tx/OSERDES_TX_DATA_00_pins<1>" PIN
        "u_lvds/uut_tx/OSERDES_TX_DATA_01_pins<1>" PIN