ddr_6to1_16chan_rt_tx.v

FPGA之间的LVDS传输

///////////////////////////////////////////////////////////////////////////////
//
//    File Name:  DDR_6TO1_16CHAN_RT_TX.v
//      Version:  1.0
//         Date:  08/07/06
//        Model:  XAPP860 LVDS Transmitter Module
//
//      Company:  Xilinx, Inc.
//  Contributor:  APD Applications Group
//
//   Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
//                INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
//                PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
//                PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
//                ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
//                APPLICATION OR STANDARD, XILINX IS MAKING NO
//                REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
//                FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
//                RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
//                REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
//                EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
//                RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
//                INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//                REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
//                FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
//                OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
//                PURPOSE.
//
//                (c) Copyright 2006 Xilinx, Inc.
//                All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
// 
// Summary:
//
// The DDR_6TO1_16CHAN_RT_TX module contains all components in the XAPP860 LVDS Transmitter,
// including 16 channels of LVDS data, one channel of LVDS clock, and a multiplexer
// that selects between a training pattern and user data.
// 
//----------------------------------------------------------------

module DDR_6TO1_16CHAN_RT_TX			
	(
	DATA_TX_P,
	DATA_TX_N,
	CLOCK_TX_P,
	CLOCK_TX_N,
	TXCLK,
	TXCLKDIV,
	DATA_TO_OSERDES,
	RESET,
	TRAINING_DONE
	);
	
input		TXCLK;			//SERIAL SIDE TX CLOCK
input		TXCLKDIV;		//PARALLEL SIDE TX CLOCK (DIVIDED FROM TXCLK)
input	[95:0]	DATA_TO_OSERDES;	//PARALLEL SIDE TX DATA
input		RESET;			//TX DOMAIN RESET
input		TRAINING_DONE;		//FLAG FROM RECEIVER INDICATING ALIGNMENT

output	[15:0]	DATA_TX_P;		//SERIAL SIDE TX DATA (P)
output	[15:0]	DATA_TX_N;		//SERIAL SIDE TX DATA (N)
output		CLOCK_TX_P;		//FORWARDED CLOCK TO RX (P)
output		CLOCK_TX_N;		//FORWARDED CLOCK TO RX (N)

wire		TX_CLOCK_PREBUF;
wire	[15:0]	TX_DATA_PREBUF;
wire	[15:0]	SHIFT1;
wire	[15:0]	SHIFT2;

reg	[95:0]	DATA_TO_OSERDES_REG;

//DATA SOURCE: TRAINING PAT OR PRBS	
//IF NO FEEDBACK CONTROLS FROM RX ARE DESIRED, THE TX CAN BE SET TO SEND THE 
//TRAINING PATTERN FOR A FIXED AMOUNT OF TIME, AFTER WHICH IT AUTOMATICALLY
//ASSUMES THAT TRAINING IS COMPLETE AND BEGINS SENDING USER DATA.
always @(posedge TXCLKDIV) begin
if (TRAINING_DONE)
	DATA_TO_OSERDES_REG <= DATA_TO_OSERDES;	//PRBS
else
	DATA_TO_OSERDES_REG <= 96'b101100101100101100101100101100101100101100101100101100101100101100101100101100101100101100101100;	//TRAINING PATTERN = 101100
end