📄 regkeys
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prop_629_namePROPEXT_xilxPARextraEffortLevel_virtex5sprop_629_val"None"sprop_62_namePROP_xstGenerateRTLNetlistsprop_62_val"Yes"sprop_630_namePROPEXT_parPowerActivityFile_virtex5sprop_630_val""sprop_631_namePROP_xilxBitgCfg_Fallback_Reconfig_virtex5sprop_631_val"Enable"sprop_632_namePROP_bitgen_Encrypt_key0_virtex5sprop_632_val""sprop_633_namePROP_bitgen_Encrypt_keyFile_virtex5sprop_633_val""sprop_634_namePROP_bitgen_Encrypt_key0sprop_634_val""sprop_635_namePROP_bitgen_Encrypt_key1sprop_635_val""sprop_636_namePROP_bitgen_Encrypt_key2sprop_636_val""sprop_637_namePROP_bitgen_Encrypt_key3sprop_637_val""sprop_638_namePROP_bitgen_Encrypt_key4sprop_638_val""sprop_639_namePROP_bitgen_Encrypt_key5sprop_639_val""sprop_63_namePROP_xstHierarchySeparatorsprop_63_val"/"sprop_640_namePROP_bitgen_Encrypt_keyFilesprop_640_val""sprop_641_namePROP_MapExtraEffortsprop_641_val"None"sprop_642_namePROP_xilxBitgCfg_GenOpt_ReadBack_virtex2sprop_642_val"false"sprop_643_namePROP_DevPackagesprop_643_val"ff1738"sprop_644_namePROP_Synthesis_Toolsprop_644_val"XST (VHDL/Verilog)"sprop_645_namePROP_CompxlibUniSimLibsprop_645_val"true"sprop_646_namePROP_CompxlibUni9000Libsprop_646_val"true"sprop_647_namePROP_xilxBitgReadBk_GenBitStr_virtex2sprop_647_val"false"sprop_648_namePROP_xilxBitgCfg_GenOpt_LogicAllocFile_virtex2sprop_648_val"false"sprop_649_namePROP_xilxBitgCfg_GenOpt_MaskFile_virtex2sprop_649_val"false"sprop_64_namePROP_xstBusDelimitersprop_64_val"<>"sprop_650_namePROP_xilxSynthAddBufrsprop_650_val"32"sprop_651_namePROP_DevSpeedsprop_651_val"-1"sprop_652_namePROP_PreferredLanguagesprop_652_val"VHDL"sprop_653_namePROP_HdlTemplateLangsprop_653_val"VHDL"sprop_654_namePROP_schFuncModelTargetLangsprop_654_val"VHDL"sprop_655_namePROP_schInstTempTargetLangsprop_655_val"VHDL"sprop_656_namePROP_hdlInstTempTargetLangsprop_656_val"VHDL"sprop_657_namePROP_ChangeDevSpeedsprop_657_val"-1"sprop_658_namePROP_SimModelTargetsprop_658_val"VHDL"sprop_659_namePROP_xawHdlSourceTargetLangsprop_659_val"VHDL"sprop_65_namePROP_SynthFsmEncodesprop_65_val"Auto"sprop_660_namePROP_tbwTestbenchTargetLangsprop_660_val"VHDL"sprop_661_namePROP_coregenFuncModelTargetLangsprop_661_val"VHDL"sprop_662_namePROP_xmpInstTempTargetLangsprop_662_val"VHDL"sprop_663_namePROP_sysgenInstTempTargetLangsprop_663_val"VHDL"sprop_664_namePROP_xilxPreTrceSpeedsprop_664_val"-1"sprop_665_namePROP_xilxPostTrceSpeedsprop_665_val"-1"sprop_666_namePROP_HdlTemplateNamesprop_666_val"xapp860.vhd"sprop_667_namePROP_SimModelRenTopLevArchTosprop_667_val"Structure"sprop_668_namePROP_SimModelGenArchOnlysprop_668_val"false"sprop_669_namePROP_SimModelOutputExtIdentsprop_669_val"false"sprop_66_namePROP_SynthCaseImplStylesprop_66_val"None"sprop_670_namePROP_SimModelRenTopLevModsprop_670_val""sprop_671_namePROP_SimModelIncUselibDirInVerilogFilesprop_671_val"false"sprop_672_namePROP_SimModelIncSdfAnnInVerilogFilesprop_672_val"true"sprop_673_namePROP_SimModelNoEscapeSignalsprop_673_val"false"sprop_674_namePROP_netgenPostXlateSimModelNamesprop_674_val"lvds_bist_top_translate.vhd"sprop_675_namePROP_netgenPostMapSimModelNamesprop_675_val"lvds_bist_top_map.vhd"sprop_676_namePROP_netgenPostParSimModelNamesprop_676_val"lvds_bist_top_timesim.vhd"sprop_677_namePROP_bencherPostXlateTestbenchNamesprop_677_val"lvds_vhd_tb.translate_vhw"sprop_678_namePROP_bencherPostMapTestbenchNamesprop_678_val"lvds_vhd_tb.map_vhw"sprop_679_namePROP_bencherPostParTestbenchNamesprop_679_val"lvds_bist_top_tb.timesim_vhw"sprop_67_namePROP_SynthResSharingsprop_67_val"true"sprop_680_namePROP_SimModelIncSimprimInVerilogFilesprop_680_val"false"sprop_681_namePROP_SimModelIncUnisimInVerilogFilesprop_681_val"false"sprop_682_namePROP_netgenPostSynthesisSimModelNamesprop_682_val"lvds_bist_top_synthesis.vhd"sprop_683_namePROP_SimModelAutoInsertGlblModuleInNetlistsprop_683_val"true"sprop_684_namePROP_PostXlateSimModelNamesprop_684_val"lvds_bist_top_translate.vhd"sprop_685_namePROP_PostXlateSimModelNamesprop_685_val"lvds_bist_top_translate.vhd"sprop_686_namePROP_PostXlateSimModelNamesprop_686_val"lvds_bist_top_translate.vhd"sprop_687_namePROP_PostXlateSimModelNamesprop_687_val"lvds_bist_top_translate.vhd"sprop_688_namePROP_PostXlateSimModelNamesprop_688_val"lvds_bist_top_translate.vhd"sprop_689_namePROP_PostXlateSimModelNamesprop_689_val"lvds_bist_top_translate.vhd"sprop_68_namePROP_SynthExtractMuxsprop_68_val"Yes"sprop_690_namePROP_PostXlateSimModelNamesprop_690_val"lvds_bist_top_translate.vhd"sprop_691_namePROP_PostXlateSimModelNamesprop_691_val"lvds_bist_top_translate.vhd"sprop_692_namePROP_PostXlateSimModelNamesprop_692_val"lvds_bist_top_translate.vhd"sprop_693_namePROP_PostMapSimModelNamesprop_693_val"lvds_bist_top_map.vhd"sprop_694_namePROP_PostMapSimModelNamesprop_694_val"lvds_bist_top_map.vhd"sprop_695_namePROP_PostMapSimModelNamesprop_695_val"lvds_bist_top_map.vhd"sprop_696_namePROP_PostMapSimModelNamesprop_696_val"lvds_bist_top_map.vhd"sprop_697_namePROP_PostMapSimModelNamesprop_697_val"lvds_bist_top_map.vhd"sprop_698_namePROP_PostMapSimModelNamesprop_698_val"lvds_bist_top_map.vhd"sprop_699_namePROP_PostMapSimModelNamesprop_699_val"lvds_bist_top_map.vhd"sprop_69_namePROP_xilxSynthAddIObufsprop_69_val"true"sprop_6_namePROP_Parse_Targetsprop_6_val"synthesis"sprop_700_namePROP_PostMapSimModelNamesprop_700_val"lvds_bist_top_map.vhd"sprop_701_namePROP_PostMapSimModelNamesprop_701_val"lvds_bist_top_map.vhd"sprop_702_namePROP_PostParSimModelNamesprop_702_val"lvds_bist_top_timesim.vhd"sprop_703_namePROP_PostParSimModelNamesprop_703_val"lvds_bist_top_timesim.vhd"sprop_704_namePROP_PostParSimModelNamesprop_704_val"lvds_bist_top_timesim.vhd"sprop_705_namePROP_PostParSimModelNamesprop_705_val"lvds_bist_top_timesim.vhd"sprop_706_namePROP_PostParSimModelNamesprop_706_val"lvds_bist_top_timesim.vhd"sprop_707_namePROP_PostParSimModelNamesprop_707_val"lvds_bist_top_timesim.vhd"sprop_708_namePROP_PostParSimModelNamesprop_708_val"lvds_bist_top_timesim.vhd"sprop_709_namePROP_PostParSimModelNamesprop_709_val"lvds_bist_top_timesim.vhd"sprop_70_namePROP_xstEquivRegRemovalsprop_70_val"true"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al"lvds_bist_top_tb.timesim_vhw"sprop_768_namePROP_tbwPostParTestbenchNamesprop_768_val"lvds_bist_top_tb.timesim_vhw"sprop_769_namePROP_PostSynthesisSimModelNamesprop_769_val"lvds_bist_top_synthesis.vhd"sprop_76_namePROP_ISimUseCustomSimCmdFile_behav_tbwsprop_76_val"false"sprop_770_namePROP_PostSynthesisSimModelNamesprop_770_val"lvds_bist_top_synthesis.vhd"sprop_771_namePROP_PostSynthesisSimModelNamesprop_771_val"lvds_bist_top_synthesis.vhd"sprop_772_namePROP_PostSynthesisSimModelNamesprop_772_val"lvds_bist_top_synthesis.vhd"sprop_773_namePROP_PostSynthesisSimModelNamesprop_773_val"lvds_bist_top_synthesis.vhd"sprop_774_namePROP_PostSynthesisSimModelNamesprop_774_val"lvds_bist_top_synthesis.vhd"sprop_775_namePROP_PostSynthesisSimModelNamesprop_775_val"lvds_bist_top_synthesis.vhd"sprop_776_namePROP_PostSynthesisSimModelNamesprop_776_val"lvds_bist_top_synthesis.vhd"sprop_777_namePROP_PostSynthesisSimModelNamesprop_777_val"lvds_bist_top_synthesis.vhd"sprop_778_namePROP_SimModelBringOutGtsNetAsAPortsprop_778_val"false"sprop_779_namePROP_SimModelBringOutGsrNetAsAPortsprop_779_val"false"sprop_77_namePROP_ISimUseCustomSimCmdFile_gen_tbwsprop_77_val"false"sprop_780_namePROP_netgenRenameTopLevEntTosprop_780_val"lvds_bist_top"sprop_781_namePROP_SimModelPathUsedInSdfAnnsprop_781_val"Default"sprop_78_namePROP_ISimUseCustomSimCmdFile_launchsprop_78_val"false"sprop_79_namePROP_isimIncreCompilationsprop_79_val"true"sprop_7_namePROP_Top_Level_Module_Typesprop_7_val"HDL"sprop_80_namePROP_isimCompileForHdlDebugsprop_80_val"true"sprop_81_namePROP_ISimSDFTimingToBeReadsprop_81_val"Setup Time"sprop_82_namePROP_isimValueRangeChecksprop_82_val"false"sprop_83_namePROP_isimSpecifySearchDirectorysprop_83_val""sprop_84_namePROP_ISimSpecifySearchDirectoryChkSyntaxsprop_84_val""sprop_85_namePROP_isimSpecifyDefMacroAndValuesprop_85_val""sprop_86_namePROP_ISimSpecifyDefMacroAndValueChkSyntaxsprop_86_val""sprop_87_namePROP_ISimLibSearchOrderFilesprop_87_val""sprop_88_namePROP_ISimUseCustomCompilationOrdersprop_88_val"false"sprop_89_namePROP_ISimOtherCompilerOptions_behavsprop_89_val""sprop_8_namePROP_SynthTopsprop_8_val"Architecture|lvds_bist_top|Behavioral"sprop_90_namePROP_ISimOtherCompilerOptions_parsprop_90_val""sprop_91_namePROP_ISimOtherCompilerOptions_fitsprop_91_val""sprop_92_namePROP_DefaultTBNamesprop_92_val"Default"sprop_93_namePROP_ibiswriterShowAllModelssprop_93_val"false"sprop_94_namePROP_ImpactProjectFilesprop_94_val"Default"sprop_95_namePROP_ngdbuild_otherCmdLineOptionssprop_95_val""sprop_96_namePROP_SynthXORCollapsesprop_96_val"true"sprop_97_namePROP_xilxNgdbld_AULsprop_97_val"false"sprop_98_namePROP_xilxNgdbldMacrosprop_98_val""sprop_99_namePROP_xilxSynthKeepHierarchysprop_99_val"Yes"sprop_9_namePROP_BehavioralSimTopsprop_9_val"Architecture|lvds_bist_top_tb|behavior"s⌨️ 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