resource_sharing_control.v

FPGA之间的LVDS传输

///////////////////////////////////////////////////////////////////////////////
//
//    File Name:  RESOURCE_SHARING_CONTROL.v
//      Version:  1.0
//         Date:  08/07/06
//        Model:  Round Robin Channel Alignment
//
//      Company:  Xilinx, Inc.
//  Contributor:  APD Applications Group
//
//   Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
//                INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
//                PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
//                PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
//                ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
//                APPLICATION OR STANDARD, XILINX IS MAKING NO
//                REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
//                FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
//                RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
//                REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
//                EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
//                RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
//                INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//                REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
//                FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
//                OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
//                PURPOSE.
//
//                (c) Copyright 2006 Xilinx, Inc.
//                All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
// 
// Summary:
//
// The RESOURCE_SHARING_CONTROL module allocates the BIT_ALIGN_MACHINE and RT_WINDOW_MONITORING
// modules to each of the 16 data channels of the interface.  Each channel 
// must be aligned one at a time, such that the RESOURCE_SHARING_CONTROL module
// must determine when training on a given channel is complete, and then 
// switch the context to the next channel. 
//
//----------------------------------------------------------------

module RESOURCE_SHARING_CONTROL
	(
	CHAN_SEL,
	ALL_CHANNELS_ALIGNED,
	DATA_ALIGNED,
	START_ALIGN,
	CLK,
	RST,
	REPEAT_PROC
	);
	
input		DATA_ALIGNED;		//FLAG: ALIGNMENT DONE ON CURRENT CHANNEL, GO TO NEXT
input		CLK;			//CLOCK
input		RST;			//RESET
input		REPEAT_PROC;		//IF SET TO 1, CAUSES PROCEDURE TO REPEAT INFINITELY

output	[3:0]	CHAN_SEL;		//VECTOR INDICATING CURRENT CHANNEL BEING ALIGNED
output		START_ALIGN;		//SIGNAL THAT ALIGNMENT PROCESS MAY BEGIN ON NEXT CHANNEL
output		ALL_CHANNELS_ALIGNED;	//SIGNAL THAT ALL CHANNELS ARE ALIGNED

wire	[6:0]	COUNT_VALUE;

reg		UD_DELAY;
reg		COUNT_DELAY;
reg		COUNT_CHAN;
reg		START_ALIGN;
reg	[2:0]	CS;
reg	[2:0]	NS;

parameter	INIT		= 3'b000;
parameter	INC_CHAN_SEL	= 3'b001;
parameter	WAIT_8		= 3'b010;
parameter	START_NEXT	= 3'b011;
parameter	LAST_CHAN	= 3'b100;
parameter	TRAIN_DONE	= 3'b101;
parameter	IDLE		= 3'b110;
parameter	START_LAST	= 3'b111;

assign		ALL_CHANNELS_ALIGNED	= CS[2] & ~CS[1] & CS[0];

count_to_128 delay_counter(.clk(CLK), .rst(RST), .count(COUNT_DELAY), .ud(UD_DELAY), .counter_value(COUNT_VALUE));
count_to_16x channel_counter(.clk(CLK), .rst(RST), .count(COUNT_CHAN), .counter_value(CHAN_SEL));

//CURRENT STATE LOGIC
always @(posedge CLK) begin
if (RST == 1'b1)
	CS <= INIT;
else
	CS <= NS;
end


//NEXT_STATE LOGIC
always @(CS or DATA_ALIGNED or COUNT_VALUE or CHAN_SEL or REPEAT_PROC) begin
case (CS)
	INIT:		begin	
			if (COUNT_VALUE < 7'h08 || DATA_ALIGNED == 1'b0)
				NS <= INIT;
			else
				NS <= IDLE;
			end
	
	IDLE:		NS <= INC_CHAN_SEL;
	
	INC_CHAN_SEL:	NS <= WAIT_8;
	
	WAIT_8:		begin
			if (COUNT_VALUE < 7'h08)
				NS <= WAIT_8;
			else
			if (CHAN_SEL == 4'b1111)
				NS <= START_LAST;
			else
				NS <= START_NEXT;
			end
	
	START_NEXT:	NS <= INIT;
	
	START_LAST:	NS <= LAST_CHAN;
	
	LAST_CHAN:	begin
			if (COUNT_VALUE < 7'h08 || DATA_ALIGNED == 1'b0)
				NS <= LAST_CHAN;
			else
				NS <= TRAIN_DONE;
			end
	
	TRAIN_DONE:	begin
			if (REPEAT_PROC == 1'b0)
				NS <= TRAIN_DONE;
			else
				NS <= INIT;
			end
			
	default:	NS <= INIT;
endcase
end

//OUTPUT LOGIC
always @(CS) begin
case (CS)
	INIT:		begin
			COUNT_CHAN	<= 1'b0;
			COUNT_DELAY 	<= 1'b1;
			UD_DELAY	<= 1'b1;
			START_ALIGN	<= 1'b0;
			end
	
	IDLE:		begin
			COUNT_CHAN	<= 1'b0;
			COUNT_DELAY 	<= 1'b0;
			UD_DELAY	<= 1'b0;
			START_ALIGN	<= 1'b0;
			end
	
	INC_CHAN_SEL:	begin
			COUNT_CHAN	<= 1'b1;
			COUNT_DELAY 	<= 1'b0;
			UD_DELAY	<= 1'b0;
			START_ALIGN	<= 1'b0;
			end
	
	WAIT_8:		begin
			COUNT_CHAN	<= 1'b0;
			COUNT_DELAY 	<= 1'b1;
			UD_DELAY	<= 1'b1;
			START_ALIGN	<= 1'b0;
			end
	
	START_NEXT:	begin
			COUNT_CHAN	<= 1'b0;
			COUNT_DELAY 	<= 1'b0;
			UD_DELAY	<= 1'b0;
			START_ALIGN	<= 1'b1;
			end
	
	START_LAST:	begin
			COUNT_CHAN	<= 1'b0;
			COUNT_DELAY 	<= 1'b0;
			UD_DELAY	<= 1'b0;
			START_ALIGN	<= 1'b1;
			end
	
	LAST_CHAN:	begin
			COUNT_CHAN	<= 1'b0;
			COUNT_DELAY 	<= 1'b1;
			UD_DELAY	<= 1'b1;
			START_ALIGN	<= 1'b0;
			end
	
	TRAIN_DONE:	begin
			COUNT_CHAN	<= 1'b0;
			COUNT_DELAY 	<= 1'b0;
			UD_DELAY	<= 1'b0;
			START_ALIGN	<= 1'b1;
			end
	
	default:	begin
			COUNT_CHAN	<= 1'b0;
			COUNT_DELAY 	<= 1'b0;
			UD_DELAY	<= 1'b0;
			START_ALIGN	<= 1'b0;
			end
endcase
end			

endmodule


module count_to_16x(clk, rst, count, counter_value);

//This module counts from 0 to 16

input clk, rst, count;
output [3:0] counter_value;

reg [3:0] counter_value_preserver;

assign counter_value = (count) ? counter_value_preserver + 1 : counter_value_preserver;

always@(posedge clk or posedge rst)
 if(rst == 1'b1)
   counter_value_preserver = 4'h0;
 else
   counter_value_preserver = counter_value;

endmodule