ddr_6to1_16chan_rt_rx.vhd

FPGA之间的LVDS传输

         ODATAIN => '0',
         DATAIN => '0',
         T => '1',
         CE => RX_DATA_CE_06,
         INC => RX_DATA_INC_06,
        C => RXCLKDIV_TEMP,
         RST => RX_DATA_RESET);   
   
   RX_DATA_CE_07 <= ICE_DELAY OR ICE_TO_ISERDES(07) OR ICE_TO_ISERDES_RT(07);
   RX_DATA_INC_07 <= INC_DELAY OR INC_TO_ISERDES(07) OR INC_TO_ISERDES_RT(07);

   IODELAY_RX_DATA_07 : IODELAY 
      GENERIC MAP(
      IDELAY_TYPE	=> "VARIABLE",
      IDELAY_VALUE	=> 0,
      ODELAY_VALUE	=> 0,
      REFCLK_FREQUENCY	=> 200.0,
      HIGH_PERFORMANCE_MODE => true
      )
      PORT MAP (
         DATAOUT => DATA_RX_IDLY(07),
         IDATAIN => DATA_RX_BUF(07),
         ODATAIN => '0',
         DATAIN => '0',
         T => '1',
         CE => RX_DATA_CE_07,
         INC => RX_DATA_INC_07,
        C => RXCLKDIV_TEMP,
         RST => RX_DATA_RESET);   
   
   RX_DATA_CE_08 <= ICE_DELAY OR ICE_TO_ISERDES(08) OR ICE_TO_ISERDES_RT(08);
   RX_DATA_INC_08 <= INC_DELAY OR INC_TO_ISERDES(08) OR INC_TO_ISERDES_RT(08);

   IODELAY_RX_DATA_08 : IODELAY 
      GENERIC MAP(
      IDELAY_TYPE	=> "VARIABLE",
      IDELAY_VALUE	=> 0,
      ODELAY_VALUE	=> 0,
      REFCLK_FREQUENCY	=> 200.0,
      HIGH_PERFORMANCE_MODE => true
      )
      PORT MAP (
         DATAOUT => DATA_RX_IDLY(08),
         IDATAIN => DATA_RX_BUF(08),
         ODATAIN => '0',
         DATAIN => '0',
         T => '1',
         CE => RX_DATA_CE_08,
         INC => RX_DATA_INC_08,
         C => RXCLKDIV_TEMP,
         RST => RX_DATA_RESET);   
   
   RX_DATA_CE_09 <= ICE_DELAY OR ICE_TO_ISERDES(09) OR ICE_TO_ISERDES_RT(09);
   RX_DATA_INC_09 <= INC_DELAY OR INC_TO_ISERDES(09) OR INC_TO_ISERDES_RT(09);

   IODELAY_RX_DATA_09 : IODELAY 
      GENERIC MAP(
      IDELAY_TYPE	=> "VARIABLE",
      IDELAY_VALUE	=> 0,
      ODELAY_VALUE	=> 0,
      REFCLK_FREQUENCY	=> 200.0,
      HIGH_PERFORMANCE_MODE => true
      )
      PORT MAP (
         DATAOUT => DATA_RX_IDLY(09),
         IDATAIN => DATA_RX_BUF(09),
         ODATAIN => '0',
         DATAIN => '0',
         T => '1',
         CE => RX_DATA_CE_09,
         INC => RX_DATA_INC_09,
         C => RXCLKDIV_TEMP,
         RST => RX_DATA_RESET);   
   
   RX_DATA_CE_10 <= ICE_DELAY OR ICE_TO_ISERDES(10) OR ICE_TO_ISERDES_RT(10);
   RX_DATA_INC_10 <= INC_DELAY OR INC_TO_ISERDES(10) OR INC_TO_ISERDES_RT(10);

   IODELAY_RX_DATA_10 : IODELAY 
      GENERIC MAP(
      IDELAY_TYPE	=> "VARIABLE",
      IDELAY_VALUE	=> 0,
      ODELAY_VALUE	=> 0,
      REFCLK_FREQUENCY	=> 200.0,
      HIGH_PERFORMANCE_MODE => true
      )
      PORT MAP (
         DATAOUT => DATA_RX_IDLY(10),
         IDATAIN => DATA_RX_BUF(10),
         ODATAIN => '0',
         DATAIN => '0',
         T => '1',
         CE => RX_DATA_CE_10,
         INC => RX_DATA_INC_10,
         C => RXCLKDIV_TEMP,
         RST => RX_DATA_RESET);   
   
   RX_DATA_CE_11 <= ICE_DELAY OR ICE_TO_ISERDES(11) OR ICE_TO_ISERDES_RT(11);
   RX_DATA_INC_11 <= INC_DELAY OR INC_TO_ISERDES(11) OR INC_TO_ISERDES_RT(11);

   IODELAY_RX_DATA_11 : IODELAY 
      GENERIC MAP(
      IDELAY_TYPE	=> "VARIABLE",
      IDELAY_VALUE	=> 0,
      ODELAY_VALUE	=> 0,
      REFCLK_FREQUENCY	=> 200.0,
      HIGH_PERFORMANCE_MODE => true
      )
      PORT MAP (
         DATAOUT => DATA_RX_IDLY(11),
         IDATAIN => DATA_RX_BUF(11),
         ODATAIN => '0',
         DATAIN => '0',
         T => '1',
         CE => RX_DATA_CE_11,
         INC => RX_DATA_INC_11,
         C => RXCLKDIV_TEMP,
         RST => RX_DATA_RESET);   
   
   RX_DATA_CE_12 <= ICE_DELAY OR ICE_TO_ISERDES(12) OR ICE_TO_ISERDES_RT(12);
   RX_DATA_INC_12 <= INC_DELAY OR INC_TO_ISERDES(12) OR INC_TO_ISERDES_RT(12);

   IODELAY_RX_DATA_12 : IODELAY 
      GENERIC MAP(
      IDELAY_TYPE	=> "VARIABLE",
      IDELAY_VALUE	=> 0,
      ODELAY_VALUE	=> 0,
      REFCLK_FREQUENCY	=> 200.0,
      HIGH_PERFORMANCE_MODE => true
      )
      PORT MAP (
         DATAOUT => DATA_RX_IDLY(12),
         IDATAIN => DATA_RX_BUF(12),
         ODATAIN => '0',
         DATAIN => '0',
         T => '1',
         CE => RX_DATA_CE_12,
         INC => RX_DATA_INC_12,
         C => RXCLKDIV_TEMP,
         RST => RX_DATA_RESET);   
   
   RX_DATA_CE_13 <= ICE_DELAY OR ICE_TO_ISERDES(13) OR ICE_TO_ISERDES_RT(13);
   RX_DATA_INC_13 <= INC_DELAY OR INC_TO_ISERDES(13) OR INC_TO_ISERDES_RT(13);

   IODELAY_RX_DATA_13 : IODELAY 
       GENERIC MAP(
      IDELAY_TYPE	=> "VARIABLE",
      IDELAY_VALUE	=> 0,
      ODELAY_VALUE	=> 0,
      REFCLK_FREQUENCY	=> 200.0,
      HIGH_PERFORMANCE_MODE => true
      )
      PORT MAP (
         DATAOUT => DATA_RX_IDLY(13),
         IDATAIN => DATA_RX_BUF(13),
         ODATAIN => '0',
         DATAIN => '0',
         T => '1',
         CE => RX_DATA_CE_13,
         INC => RX_DATA_INC_13,
         C => RXCLKDIV_TEMP,
         RST => RX_DATA_RESET);   
   
   RX_DATA_CE_14 <= ICE_DELAY OR ICE_TO_ISERDES(14) OR ICE_TO_ISERDES_RT(14);
   RX_DATA_INC_14 <= INC_DELAY OR INC_TO_ISERDES(14) OR INC_TO_ISERDES_RT(14);

   IODELAY_RX_DATA_14 : IODELAY 
      GENERIC MAP(
      IDELAY_TYPE	=> "VARIABLE",
      IDELAY_VALUE	=> 0,
      ODELAY_VALUE	=> 0,
      REFCLK_FREQUENCY	=> 200.0,
      HIGH_PERFORMANCE_MODE => true
      )
      PORT MAP (
         DATAOUT => DATA_RX_IDLY(14),
         IDATAIN => DATA_RX_BUF(14),
         ODATAIN => '0',
         DATAIN => '0',
         T => '1',
         CE => RX_DATA_CE_14,
         INC => RX_DATA_INC_14,
         C => RXCLKDIV_TEMP,
         RST => RX_DATA_RESET);   
   
   RX_DATA_CE_15 <= ICE_DELAY OR ICE_TO_ISERDES(15) OR ICE_TO_ISERDES_RT(15);
   RX_DATA_INC_15 <= INC_DELAY OR INC_TO_ISERDES(15) OR INC_TO_ISERDES_RT(15);

   IODELAY_RX_DATA_15 : IODELAY 
       GENERIC MAP(
      IDELAY_TYPE	=> "VARIABLE",
      IDELAY_VALUE	=> 0,
      ODELAY_VALUE	=> 0,
      REFCLK_FREQUENCY	=> 200.0,
      HIGH_PERFORMANCE_MODE => true
      )
      PORT MAP (
         DATAOUT => DATA_RX_IDLY(15),
         IDATAIN => DATA_RX_BUF(15),
         ODATAIN => '0',
         DATAIN => '0',
         T => '1',
         CE => RX_DATA_CE_15,
         INC => RX_DATA_INC_15,
         C => RXCLKDIV_TEMP,
         RST => RX_DATA_RESET);   
   
	RX_DATA_CE_16 <= ICE_DELAY OR ICE_TO_ISERDES(16) OR ICE_TO_ISERDES_RT(16);
   RX_DATA_INC_16 <= INC_DELAY OR INC_TO_ISERDES(16) OR INC_TO_ISERDES_RT(16);

   IODELAY_RX_CNTL : IODELAY 
       GENERIC MAP(
      IDELAY_TYPE	=> "VARIABLE",
      IDELAY_VALUE	=> 0,
      ODELAY_VALUE	=> 0,
      REFCLK_FREQUENCY	=> 200.0,
      HIGH_PERFORMANCE_MODE => true
      )
      PORT MAP (
         DATAOUT => DATA_RX_IDLY(16),
         IDATAIN => DATA_RX_BUF(16),
         ODATAIN => '0',
         DATAIN => '0',
         T => '1',
         CE => RX_DATA_CE_16,
         INC => RX_DATA_INC_16,
         C => RXCLKDIV_TEMP,
         RST => RX_DATA_RESET); 

   --MASTER SIDE ISERDES                                                                                                    

   BITSLIP_00 <= BITSLIP_PULSE OR BITSLIP_TO_ISERDES(00);

   ISERDES_RX_DATA_00 : ISERDES_NODELAY 
   GENERIC MAP(
         BITSLIP_ENABLE => TRUE, DATA_RATE => "DDR", DATA_WIDTH => 4, 
         INTERFACE_TYPE => "NETWORKING", NUM_CE => 1, SERDES_MODE =>"MASTER")
      PORT MAP (
         --Q1 => DATA_FROM_ISERDES_TEMP(005),
         --Q2 => DATA_FROM_ISERDES_TEMP(004),
         Q3 => DATA_FROM_ISERDES_TEMP(003),
         Q4 => DATA_FROM_ISERDES_TEMP(002),
         Q5 => DATA_FROM_ISERDES_TEMP(001),
         Q6 => DATA_FROM_ISERDES_TEMP(000),
         SHIFTOUT1 => open,
         SHIFTOUT2 => open,
         BITSLIP => BITSLIP_00,
         CE1 => '1',
         CE2 => '0',
         CLK => RXCLK_TEMP,
         CLKB => NOT_RXCLK_TEMP,
         CLKDIV => RXCLKDIV_TEMP,
         D => DATA_RX_IDLY(00),
         OCLK => '0',
         SHIFTIN1 => '0',
         SHIFTIN2 => '0',
         RST => RESET);   
   
  BITSLIP_01 <= BITSLIP_PULSE OR BITSLIP_TO_ISERDES(01);

   ISERDES_RX_DATA_01 : ISERDES_NODELAY 
   GENERIC MAP(
         BITSLIP_ENABLE => TRUE, DATA_RATE => "DDR", DATA_WIDTH => 4,  
         INTERFACE_TYPE => "NETWORKING", NUM_CE => 1, SERDES_MODE =>"MASTER")
      PORT MAP (
         --Q1 => DATA_FROM_ISERDES_TEMP(011),
         --Q2 => DATA_FROM_ISERDES_TEMP(010),
         Q3 => DATA_FROM_ISERDES_TEMP(007),
         Q4 => DATA_FROM_ISERDES_TEMP(006),
         Q5 => DATA_FROM_ISERDES_TEMP(005),
         Q6 => DATA_FROM_ISERDES_TEMP(004),
         SHIFTOUT1 => open,
         SHIFTOUT2 => open,
         BITSLIP => BITSLIP_01,
         CE1 => '1',
         CE2 => '0',
         CLK => RXCLK_TEMP,
         CLKB => NOT_RXCLK_TEMP,
         CLKDIV => RXCLKDIV_TEMP,
         D => DATA_RX_IDLY(01),
         OCLK => '0',
         SHIFTIN1 => '0',
         SHIFTIN2 => '0',
         RST => RESET);   
   
   BITSLIP_02 <= BITSLIP_PULSE OR BITSLIP_TO_ISERDES(02);

   ISERDES_RX_DATA_02 : ISERDES_NODELAY 
   GENERIC MAP(
         BITSLIP_ENABLE => TRUE, DATA_RATE => "DDR", DATA_WIDTH => 4,  
         INTERFACE_TYPE => "NETWORKING", NUM_CE => 1, SERDES_MODE =>"MASTER")
      PORT MAP (
         --Q1 => DATA_FROM_ISERDES_TEMP(017),
         --Q2 => DATA_FROM_ISERDES_TEMP(016),
         Q3 => DATA_FROM_ISERDES_TEMP(011),
         Q4 => DATA_FROM_ISERDES_TEMP(010),
         Q5 => DATA_FROM_ISERDES_TEMP(009),
         Q6 => DATA_FROM_ISERDES_TEMP(008),
         SHIFTOUT1 => open,
         SHIFTOUT2 => open,
         BITSLIP => BITSLIP_02,
         CE1 => '1',
         CE2 => '0',
         CLK => RXCLK_TEMP,
         CLKB => NOT_RXCLK_TEMP,
         CLKDIV => RXCLKDIV_TEMP,
         D => DATA_RX_IDLY(02),
         OCLK => '0',
         SHIFTIN1 => '0',
         SHIFTIN2 => '0',
         RST => RESET);   
   
   BITSLIP_03 <= BITSLIP_PULSE OR BITSLIP_TO_ISERDES(03);

   ISERDES_RX_DATA_03 : ISERDES_NODELAY 
   GENERIC MAP(
         BITSLIP_ENABLE => TRUE, DATA_RATE => "DDR", DATA_WIDTH => 4, 
         INTERFACE_TYPE => "NETWORKING", NUM_CE => 1, SERDES_MODE =>"MASTER")
      PORT MAP (
         --Q1 => DATA_FROM_ISERDES_TEMP(023),
         --Q2 => DATA_FROM_ISERDES_TEMP(022),
         Q3 => DATA_FROM_ISERDES_TEMP(015),
         Q4 => DATA_FROM_ISERDES_TEMP(014),
         Q5 => DATA_FROM_ISERDES_TEMP(013),
         Q6 => DATA_FROM_ISERDES_TEMP(012),
         SHIFTOUT1 => open,
         SHIFTOUT2 => open,
         BITSLIP => BITSLIP_03,
         CE1 => '1',
         CE2 => '0',
         CLK => RXCLK_TEMP,
         CLKB => NOT_RXCLK_TEMP,
         CLKDIV => RXCLKDIV_TEMP,
         D => DATA_RX_IDLY(03),
         OCLK => '0',
         SHIFTIN1 => '0',
         SHIFTIN2 =