ddr_6to1_16chan_rt_rx.vhd

来自「FPGA之间的LVDS传输」· VHDL 代码 · 共 1,696 行 · 第 1/5 页

signal RST_BIT_ALIGN_MACHINE:std_logic;
--SIGNAL RXCLK_USR_BUF					: std_logic;
--SIGNAL RXCLKDIV	: std_logic;

attribute DIFF_TERM : string;  
attribute DIFF_TERM of RX_DATA_IN_00  : label is "TRUE";
attribute DIFF_TERM of RX_DATA_IN_01  : label is "TRUE";
attribute DIFF_TERM of RX_DATA_IN_02  : label is "TRUE";
attribute DIFF_TERM of RX_DATA_IN_03  : label is "TRUE";
attribute DIFF_TERM of RX_DATA_IN_04  : label is "TRUE";
attribute DIFF_TERM of RX_DATA_IN_05  : label is "TRUE";
attribute DIFF_TERM of RX_DATA_IN_06  : label is "TRUE";
attribute DIFF_TERM of RX_DATA_IN_07  : label is "TRUE";
attribute DIFF_TERM of RX_DATA_IN_08  : label is "TRUE";
attribute DIFF_TERM of RX_DATA_IN_09  : label is "TRUE";
attribute DIFF_TERM of RX_DATA_IN_10  : label is "TRUE";
attribute DIFF_TERM of RX_DATA_IN_11  : label is "TRUE";
attribute DIFF_TERM of RX_DATA_IN_12  : label is "TRUE";
attribute DIFF_TERM of RX_DATA_IN_13  : label is "TRUE";
attribute DIFF_TERM of RX_DATA_IN_14  : label is "TRUE";
attribute DIFF_TERM of RX_DATA_IN_15  : label is "TRUE";
attribute DIFF_TERM of RX_CNTL  : label is "TRUE";

BEGIN
   DATA_FROM_ISERDES <= DATA_FROM_ISERDES_TEMP;
   --RXCLK <= RXCLK_TEMP;
	NOT_RXCLK_TEMP <= not RXCLK_TEMP;

   TRAINING_DONE <= TRAINING_DONE_TEMP;

   INC_DELAY <= INC_PULSE ;
   ICE_DELAY <= INC_PULSE OR DEC_PULSE ;
--	OBUF_i : OBUF
--		PORT MAP (
--         I => RXCLK_TEMP,
--         O => RXCLK);   
   
RXCLKDIV <= RXCLKDIV_TEMP;

   --IDELAYCTRL MODULE

	--wr_en <= DATA_FROM_ISERDES(3) and DATA_FROM_ISERDES(2) and DATA_FROM_ISERDES(1) and DATA_FROM_ISERDES(0);
	--wr_en <= DATA_FROM_ISERDES(2) ;
	--rd_en <= not empty;
	
--	U_IBUFG: IBUFG
--	PORT MAP
--	(
--		I=> RXCLK_USR,
--		O => RXCLK_USR_BUF
--	);
	
		process(RXCLK_USR)
	begin
		IF (RXCLK_USR'EVENT AND RXCLK_USR = '1') THEN
				rd_en <= not almost_empty;
				rd_en_reg <= rd_en;
	    END IF;
   END PROCESS;
	
	
	process(RXCLK_USR)
	begin
		IF (RXCLK_USR'EVENT AND RXCLK_USR = '1') THEN
				--DATA_RX_FIFO_VLD <=rd_en;
				DATA_RX_FIFO_VLD <= rd_en_reg;	--to meet timing for 200MHz timing, adjust if other freq
				DATA_RX_FIFO <= dout;
      END IF;
   END PROCESS;
	
	process(RXCLKDIV_TEMP)
	begin
		IF (RXCLKDIV_TEMP'EVENT AND RXCLKDIV_TEMP = '1') THEN
				din <= DATA_FROM_ISERDES(63 downto 0);
				wr_en <= DATA_FROM_ISERDES(64) and DATA_FROM_ISERDES(65) and DATA_FROM_ISERDES(66) and DATA_FROM_ISERDES(67) and TRAINING_DONE_TEMP ;				
      END IF;
   END PROCESS;
   
	U_FIFO : fifo_rx 
		port map(
		din => din,
		rd_clk => RXCLK_USR,
		rd_en	=> rd_en,
		rst => RESET,
		wr_clk =>RXCLKDIV_TEMP,
		wr_en =>wr_en,
		almost_empty =>almost_empty,
		almost_full =>open,
		dout  => dout,
		empty => open,
		full => open);
	
	RX_IDELAYCTRL : IDELAYCTRL 
      PORT MAP (
         RDY => IDELAY_READY,
         REFCLK => CLK200,
         RST => IDELAYCTRL_RESET);   
   
   
   --SOURCE SYNCHRONOUS CLOCK INPUT

   SOURCE_SYNC_CLOCK_IN : IBUFDS 
      GENERIC MAP(
         DIFF_TERM => TRUE, IOSTANDARD =>"LVDS_25") 
      PORT MAP (
         O => CLOCK_RX_BUF,
         I => CLOCK_RX_P,
         IB => CLOCK_RX_N);   
   
   
   --IDELAY IN CLOCK PATH

   ISERDES_CLOCK_RX : IODELAY 
      GENERIC MAP(
         IDELAY_TYPE => "FIXED", IDELAY_VALUE => 0, 
         ODELAY_VALUE => 0, REFCLK_FREQUENCY => 200.00,  
        HIGH_PERFORMANCE_MODE => true) 
      PORT MAP (
         DATAOUT => CLOCK_RX_ISERDES_OUT,
         IDATAIN => CLOCK_RX_BUF,
         ODATAIN => '0',
         DATAIN => '0',
         T => '1',
         CE => '0',
         INC => '0',
         C => '0',
         RST => RESET);   
   
   
   --CLOCK BUFFER FOR SERIAL SIDE CLOCK	

   RX_CLK_BUFIO : BUFIO 
      PORT MAP (
         O => RXCLK_TEMP,
         I => CLOCK_RX_ISERDES_OUT);   
   
   
   --CLOCK BUFFER/DIVIDER FOR PARALLEL SIDE CLOCK

   --RX_CLK_BUFR : BUFR 
   --   GENERIC MAP( 
   --      BUFR_DIVIDE => "2" )
   --   PORT MAP (
   --      O => RXCLKDIV_TEMP,
   --      CE => '1',
   --     CLR => '0',
   --      I => CLOCK_RX_ISERDES_OUT);  

   process(CLOCK_RX_ISERDES_OUT)
	begin
		if CLOCK_RX_ISERDES_OUT'event and CLOCK_RX_ISERDES_OUT='1' then
			RXCLKDIV_TEMP<=not RXCLKDIV_TEMP;
		end if;
	end process;
   

   -- CHANNEL SELECT LOGIC TO SHARE ALIGNMENT MACHINE 
   -- RESOURCES IN ROUND ROBIN FASHION
   
   PROCESS (RXCLKDIV_TEMP)
   BEGIN
      IF (RXCLKDIV_TEMP'EVENT AND RXCLKDIV_TEMP = '1') THEN
         CASE CHAN_SEL IS
            WHEN "00000" =>
                  DATA_TO_MACHINE <= DATA_FROM_ISERDES_TEMP(3 DOWNTO 0);    
                  INC_TO_ISERDES <= "0000000000000000" & INC_FROM_MACHINE;    
                  ICE_TO_ISERDES <= "0000000000000000" & ICE_FROM_MACHINE;    
                  BITSLIP_TO_ISERDES <= "0000000000000000" &    
                                           BITSLIP_FROM_MACHINE;    
            WHEN "00001" =>
                  DATA_TO_MACHINE <= DATA_FROM_ISERDES_TEMP(7 DOWNTO 4);    
                  INC_TO_ISERDES <= "000000000000000" & INC_FROM_MACHINE & '0';    
                  ICE_TO_ISERDES <= "000000000000000" & ICE_FROM_MACHINE & '0';    
                  BITSLIP_TO_ISERDES <= "000000000000000" & 
                     BITSLIP_FROM_MACHINE & '0';    
            WHEN "00010" =>
                  DATA_TO_MACHINE <= DATA_FROM_ISERDES_TEMP(11 DOWNTO 8);    
                  INC_TO_ISERDES <= "00000000000000" & INC_FROM_MACHINE & "00";    
                  ICE_TO_ISERDES <= "00000000000000" & ICE_FROM_MACHINE & "00";    
                  BITSLIP_TO_ISERDES <= "00000000000000" & 
                     BITSLIP_FROM_MACHINE & "00";    
            WHEN "00011" =>
                  DATA_TO_MACHINE <= DATA_FROM_ISERDES_TEMP(15 DOWNTO 12);    
                  INC_TO_ISERDES <= "0000000000000" & INC_FROM_MACHINE & "000";    
                  ICE_TO_ISERDES <= "0000000000000" & ICE_FROM_MACHINE & "000";    
                  BITSLIP_TO_ISERDES <= "0000000000000" & 
                     BITSLIP_FROM_MACHINE & "000";    
            WHEN "00100" =>
                  DATA_TO_MACHINE <= DATA_FROM_ISERDES_TEMP(19 DOWNTO 16);    
                  INC_TO_ISERDES <= "000000000000" & INC_FROM_MACHINE & "0000";    
                  ICE_TO_ISERDES <= "000000000000" & ICE_FROM_MACHINE & "0000";    
                  BITSLIP_TO_ISERDES <= "000000000000" & 
                     BITSLIP_FROM_MACHINE & "0000";    
            WHEN "00101" =>
                  DATA_TO_MACHINE <= DATA_FROM_ISERDES_TEMP(23 DOWNTO 20);    
                  INC_TO_ISERDES <= "00000000000" & INC_FROM_MACHINE & "00000";    
                  ICE_TO_ISERDES <= "00000000000" & ICE_FROM_MACHINE & "00000";    
                  BITSLIP_TO_ISERDES <= "00000000000" & 
                     BITSLIP_FROM_MACHINE & "00000";    
            WHEN "00110" =>
                  DATA_TO_MACHINE <= DATA_FROM_ISERDES_TEMP(27 DOWNTO 24);    
                  INC_TO_ISERDES <= "0000000000" & INC_FROM_MACHINE & "000000";    
                  ICE_TO_ISERDES <= "0000000000" & ICE_FROM_MACHINE & "000000";    
                  BITSLIP_TO_ISERDES <= "0000000000" & 
                     BITSLIP_FROM_MACHINE & "000000";    
            WHEN "00111" =>
                  DATA_TO_MACHINE <= DATA_FROM_ISERDES_TEMP(31 DOWNTO 28);    
                  INC_TO_ISERDES <= "000000000" & INC_FROM_MACHINE & "0000000";    
                  ICE_TO_ISERDES <= "000000000" & ICE_FROM_MACHINE & "0000000";    
                  BITSLIP_TO_ISERDES <= "000000000" & 
                     BITSLIP_FROM_MACHINE & "0000000";    
            WHEN "01000" =>
                  DATA_TO_MACHINE <= DATA_FROM_ISERDES_TEMP(35 DOWNTO 32);    
                  INC_TO_ISERDES <= "00000000" & INC_FROM_MACHINE & "00000000";    
                  ICE_TO_ISERDES <= "00000000" & ICE_FROM_MACHINE & "00000000";    
                  BITSLIP_TO_ISERDES <= "00000000" & 
                     BITSLIP_FROM_MACHINE & "00000000";    
            WHEN "01001" =>
                  DATA_TO_MACHINE <= DATA_FROM_ISERDES_TEMP(39 DOWNTO 36);    
                  INC_TO_ISERDES <= "0000000" & INC_FROM_MACHINE & "000000000";    
                  ICE_TO_ISERDES <= "0000000" & ICE_FROM_MACHINE & "000000000";    
                  BITSLIP_TO_ISERDES <= "0000000" & 
                     BITSLIP_FROM_MACHINE & "000000000";    
            WHEN "01010" =>
                  DATA_TO_MACHINE <= DATA_FROM_ISERDES_TEMP(43 DOWNTO 40);    
                  INC_TO_ISERDES <= "000000" & INC_FROM_MACHINE & "0000000000";    
                  ICE_TO_ISERDES <= "000000" & ICE_FROM_MACHINE & "0000000000";    
                  BITSLIP_TO_ISERDES <= "000000" & 
                     BITSLIP_FROM_MACHINE & "0000000000";    
            WHEN "01011" =>
                  DATA_TO_MACHINE <= DATA_FROM_ISERDES_TEMP(47 DOWNTO 44);    
                  INC_TO_ISERDES <= "00000" & INC_FROM_MACHINE & "00000000000";    
                  ICE_TO_ISERDES <= "00000" & ICE_FROM_MACHINE & "00000000000";    
                  BITSLIP_TO_ISERDES <= "00000" & BITSLIP_FROM_MACHINE 
                     & "00000000000";    
            WHEN "01100" =>
                  DATA_TO_MACHINE <= DATA_FROM_ISERDES_TEMP(51 DOWNTO 48);    
                  INC_TO_ISERDES <= "0000" & INC_FROM_MACHINE & "000000000000";    
                  ICE_TO_ISERDES <= "0000" & ICE_FROM_MACHINE & "000000000000";    
                  BITSLIP_TO_ISERDES <= "0000" & BITSLIP_FROM_MACHINE 
                     & "000000000000";    
            WHEN "01101" =>
                  DATA_TO_MACHINE <= DATA_FROM_ISERDES_TEMP(55 DOWNTO 52);    
                  INC_TO_ISERDES <= "000" & INC_FROM_MACHINE & "0000000000000";    
                  ICE_TO_ISERDES <= "000" & ICE_FROM_MACHINE & "0000000000000";    
                  BITSLIP_TO_ISERDES <= "000" & BITSLIP_FROM_MACHINE & 
                     "0000000000000";    
            WHEN "01110" =>
                  DATA_TO_MACHINE <= DATA_FROM_ISERDES_TEMP(59 DOWNTO 56);    
                  INC_TO_ISERDES <= "00" & INC_FROM_MACHINE & "00000000000000";    
                  ICE_TO_ISERDES <= "00" & ICE_FROM_MACHINE & "00000000000000";    
                  BITSLIP_TO_ISERDES <= "00" & BITSLIP_FROM_MACHINE & 
                     "00000000000000";    
            WHEN "01111" =>
                  DATA_TO_MACHINE <= DATA_FROM_ISERDES_TEMP(63 DOWNTO 60);    
                  INC_TO_ISERDES <= '0' & INC_FROM_MACHINE & "000000000000000";    
                  ICE_TO_ISERDES <= '0' &ICE_FROM_MACHINE & "000000000000000";    
                  BITSLIP_TO_ISERDES <= '0' & BITSLIP_FROM_MACHINE & 
                     "000000000000000";
				WHEN "10000" =>
                  DATA_TO_MACHINE <= DATA_FROM_ISERDES_TEMP(67 DOWNTO 64);    
                  INC_TO_ISERDES <=   INC_FROM_MACHINE & "0000000000000000";    
                  ICE_TO_ISERDES <=  ICE_FROM_MACHINE & "0000000000000000";    
                  BITSLIP_TO_ISERDES <=  BITSLIP_FROM_MACHINE & 
                     "0000000000000000";
            WHEN OTHERS => NULL;
            
         END CASE;
      END IF;
   END PROCESS;

--MACHINE THAT ALLOCATES BIT_ALIGN_MACHINE TO EACH OF THE 16 DATA CHANNELS, ONE --AT A TIME 
   RESOURCE_SHARING_CONTROL_0 : RESOURCE_SHARING_CONTROL 
      PORT MAP (
         CHAN_SEL => CHAN_SEL,
         ALL_CHANNELS_ALIGNED => TRAINING_DONE_TEMP,
         DATA_ALIGNED => DATA_ALIGNED,
         START_ALIGN => START_ALIGN,
         CLK => RXCLKDIV_TEMP,
         RST => RESET,
         REPEAT_PROC => '0');   
   

		 BIT_ALIGN_MACHINE_RESET <= RESET OR RESET_SM(15);

--MACHINE THAT ADJUSTS DELAY OF A SINGLE DATA CHANNEL TO OPTIMIZE SAMPLING POINT 
   BIT_ALIGN_MACHINE_0 : BIT_ALIGN_MACHINE 
      PORT MAP (
         RXCLKDIV => RXCLKDIV_TEMP,
         RXDATA => DATA_TO_MACHINE,
         RST => BIT_ALIGN_MACHINE_RESET,
         USE_BITSLIP => '1',
         SAP => START_ALIGN,
         INC => INC_FROM_MACHINE,
         ICE => ICE_FROM_MACHINE,
         BITSLIP => BITSLIP_FROM_MACHINE,
         DATA_ALIGNED => DATA_ALIGNED);   
   
--MACHINE THAT ALLOCATES RT_WINDOW_MONITOR TO EACH OF THE 16 DATA CHANNELS, ONE --AT A TIME 
   RESOURCE_SHARING_CONTROL_1 : RESOURCE_SHARING_CONTROL 
      PORT MAP (
         CHAN_SEL => CHAN_SEL_RT,
         ALL_CHANNELS_ALIGNED => open,
         DATA_ALIGNED => DATA_ALIGNED_RT,
         START_ALIGN => START_ALIGN_RT,
         CLK => RXCLKDIV_TEMP,
         RST => RESET,
         REPEAT_PROC => '1');   
   
--MACHINE THAT ADJUSTS DATA CHANNEL DELAYS IN REAL-TIME TO ACCOUNT FOR VT 
--VARIATION

RT_WINDOW_MONITOR_TRAINING <= (TRAINING_DONE_TEMP AND RT_MANUAL_DISABLE);

   RT_WINDOW_MONITOR_0 : RT_WINDOW_MONITOR 
      PORT MAP (
         CLOCK => RXCLKDIV_TEMP,
         RESET => RESET,
         TRAINING_DONE => RT_WINDOW_MONITOR_TRAINING,
         START => START_ALIGN_RT,
         DATA_MASTER => DATA_TO_RT,
         DATA_MONITOR => MONITOR_TO_RT,
         INC_MONITOR => INC_MONITOR,
         ICE_MONITOR => ICE_MONITOR,
         INC_DATABUS => INC_DATABUS,
         ICE_DATABUS => ICE_DATABUS,
         DATA_ALIGNED_RT => DATA_ALIGNED_RT);   
   

   --CHANNEL SELECT LOGIC TO SHARE RT_WINDOW_MONITOR IN ROUND ROBIN FASHION
   
   PROCESS (RXCLKDIV_TEMP)
   BEGIN
      IF (RXCLKDIV_TEMP'EVENT AND RXCLKDIV_TEMP  = '1') THEN
         CASE CHAN_SEL_RT IS
            WHEN "00000" =>
                     DATA_TO_RT <= DATA_FROM_ISERDES_TEMP(3 DOWNTO 0);  
                     MONITOR_TO_RT <= DATA_FROM_ISERDES_MON(3 DOWNTO 0); 
                     INC_TO_ISERDES_RT <= "0000000000000000" & INC_DATABUS;    
                     ICE_TO_ISERDES_RT <= "0000000000000000" & ICE_DATABUS;