ddr_6to1_16chan_rt_rx.v3

FPGA之间的LVDS传输

			INC_TO_MONITOR_RT <= {10'b0000000000, INC_MONITOR, 5'b00000};
			ICE_TO_MONITOR_RT <= {10'b0000000000, ICE_MONITOR, 5'b00000};
			end
	
	4'b0110: 	begin
			DATA_TO_RT <= DATA_FROM_ISERDES[41:36];
			MONITOR_TO_RT <= DATA_FROM_ISERDES_MON[41:36];
			INC_TO_ISERDES_RT <= {9'b000000000, INC_DATABUS, 6'b000000};
			ICE_TO_ISERDES_RT <= {9'b000000000, ICE_DATABUS, 6'b000000};
			INC_TO_MONITOR_RT <= {9'b000000000, INC_MONITOR, 6'b000000};
			ICE_TO_MONITOR_RT <= {9'b000000000, ICE_MONITOR, 6'b000000};
			end
	
	4'b0111: 	begin
			DATA_TO_RT <= DATA_FROM_ISERDES[47:42];
			MONITOR_TO_RT <= DATA_FROM_ISERDES_MON[47:42];
			INC_TO_ISERDES_RT <= {8'b00000000, INC_DATABUS, 7'b0000000};
			ICE_TO_ISERDES_RT <= {8'b00000000, ICE_DATABUS, 7'b0000000};
			INC_TO_MONITOR_RT <= {8'b00000000, INC_MONITOR, 7'b0000000};
			ICE_TO_MONITOR_RT <= {8'b00000000, ICE_MONITOR, 7'b0000000};
			end
			
	4'b1000: 	begin
			DATA_TO_RT <= DATA_FROM_ISERDES[53:48];
			MONITOR_TO_RT <= DATA_FROM_ISERDES_MON[53:48];
			INC_TO_ISERDES_RT <= {7'b0000000, INC_DATABUS, 8'b00000000};
			ICE_TO_ISERDES_RT <= {7'b0000000, ICE_DATABUS, 8'b00000000};
			INC_TO_MONITOR_RT <= {7'b0000000, INC_MONITOR, 8'b00000000};
			ICE_TO_MONITOR_RT <= {7'b0000000, ICE_MONITOR, 8'b00000000};
			end
			
	4'b1001: 	begin
			DATA_TO_RT <= DATA_FROM_ISERDES[59:54];
			MONITOR_TO_RT <= DATA_FROM_ISERDES_MON[59:54];
			INC_TO_ISERDES_RT <= {6'b000000, INC_DATABUS, 9'b000000000};
			ICE_TO_ISERDES_RT <= {6'b000000, ICE_DATABUS, 9'b000000000};
			INC_TO_MONITOR_RT <= {6'b000000, INC_MONITOR, 9'b000000000};
			ICE_TO_MONITOR_RT <= {6'b000000, ICE_MONITOR, 9'b000000000};
			end
	
	4'b1010: 	begin
			DATA_TO_RT <= DATA_FROM_ISERDES[65:60];
			MONITOR_TO_RT <= DATA_FROM_ISERDES_MON[65:60];
			INC_TO_ISERDES_RT <= {5'b00000, INC_DATABUS, 10'b0000000000};
			ICE_TO_ISERDES_RT <= {5'b00000, ICE_DATABUS, 10'b0000000000};
			INC_TO_MONITOR_RT <= {5'b00000, INC_MONITOR, 10'b0000000000};
			ICE_TO_MONITOR_RT <= {5'b00000, ICE_MONITOR, 10'b0000000000};
			end
	
	4'b1011: 	begin
			DATA_TO_RT <= DATA_FROM_ISERDES[71:66];
			MONITOR_TO_RT <= DATA_FROM_ISERDES_MON[71:66];
			INC_TO_ISERDES_RT <= {4'b0000, INC_DATABUS, 11'b00000000000};
			ICE_TO_ISERDES_RT <= {4'b0000, ICE_DATABUS, 11'b00000000000};
			INC_TO_MONITOR_RT <= {4'b0000, INC_MONITOR, 11'b00000000000};
			ICE_TO_MONITOR_RT <= {4'b0000, ICE_MONITOR, 11'b00000000000};
			end
	
	4'b1100: 	begin
			DATA_TO_RT <= DATA_FROM_ISERDES[77:72];
			MONITOR_TO_RT <= DATA_FROM_ISERDES_MON[77:72];
			INC_TO_ISERDES_RT <= {3'b000, INC_DATABUS, 12'b000000000000};
			ICE_TO_ISERDES_RT <= {3'b000, ICE_DATABUS, 12'b000000000000};
			INC_TO_MONITOR_RT <= {3'b000, INC_MONITOR, 12'b000000000000};
			ICE_TO_MONITOR_RT <= {3'b000, ICE_MONITOR, 12'b000000000000};
			end
	
	4'b1101: 	begin
			DATA_TO_RT <= DATA_FROM_ISERDES[83:78];
			MONITOR_TO_RT <= DATA_FROM_ISERDES_MON[83:78];
			INC_TO_ISERDES_RT <= {2'b00, INC_DATABUS, 13'b0000000000000};
			ICE_TO_ISERDES_RT <= {2'b00, ICE_DATABUS, 13'b0000000000000};
			INC_TO_MONITOR_RT <= {2'b00, INC_MONITOR, 13'b0000000000000};
			ICE_TO_MONITOR_RT <= {2'b00, ICE_MONITOR, 13'b0000000000000};
			end
			
	4'b1110: 	begin
			DATA_TO_RT <= DATA_FROM_ISERDES[89:84];
			MONITOR_TO_RT <= DATA_FROM_ISERDES_MON[89:84];
			INC_TO_ISERDES_RT <= {1'b0, INC_DATABUS, 14'b00000000000000};
			ICE_TO_ISERDES_RT <= {1'b0, ICE_DATABUS, 14'b00000000000000};
			INC_TO_MONITOR_RT <= {1'b0, INC_MONITOR, 14'b00000000000000};
			ICE_TO_MONITOR_RT <= {1'b0, ICE_MONITOR, 14'b00000000000000};
			end
			
	4'b1111: 	begin
			DATA_TO_RT <= DATA_FROM_ISERDES[95:90];
			MONITOR_TO_RT <= DATA_FROM_ISERDES_MON[95:90];
			INC_TO_ISERDES_RT <= {INC_DATABUS, 15'b000000000000000};
			ICE_TO_ISERDES_RT <= {ICE_DATABUS, 15'b000000000000000};
			INC_TO_MONITOR_RT <= {INC_MONITOR, 15'b000000000000000};
			ICE_TO_MONITOR_RT <= {ICE_MONITOR, 15'b000000000000000};
			end
endcase
end

 
//SHORTEN EACH EXTERNAL INC AND DEC PULSE TO ONE RXCLKDIV CYCLE
always @(posedge RXCLKDIV)
   begin						
      INC_CAPTURE[0] <= INC_PAD;			//ASYNCHRONOUS ENTRY POINT
      DEC_CAPTURE[0] <= DEC_PAD;
      BITSLIP_CAPTURE[0] <= BITSLIP_PAD;
      begin
         for(I = 0; I <= 3 - 1; I = I + 1)
         begin
            INC_CAPTURE[I + 1] <= INC_CAPTURE[I];	//METASTABLE FLIP-FLOPS
            DEC_CAPTURE[I + 1] <= DEC_CAPTURE[I];	
            BITSLIP_CAPTURE[I + 1] <= BITSLIP_CAPTURE[I];	
         end
      end
      INC_PULSE <= INC_CAPTURE[2] & ~INC_CAPTURE[3];	//STABLE, SINGLE PULSE
      DEC_PULSE <= DEC_CAPTURE[2] & ~DEC_CAPTURE[3];	
      BITSLIP_PULSE <= BITSLIP_CAPTURE[2] & ~BITSLIP_CAPTURE[3];
   end
   
//KEEP TRACK OF CURRENT TAP SETTING OF IDELAY IN DATA PATH OF CHANNELS 0-15
COUNT_TO_64 TAP_COUNTER_00(.clk(RXCLKDIV), .rst(IDLY_RESET||RESET), .count(ICE_DELAY||ICE_TO_ISERDES[00]||ICE_TO_ISERDES_RT[00]), .ud(INC_DELAY||INC_TO_ISERDES[00]||INC_TO_ISERDES_RT[00]), .counter_value(TAP_00));
COUNT_TO_64 TAP_COUNTER_01(.clk(RXCLKDIV), .rst(IDLY_RESET||RESET), .count(ICE_DELAY||ICE_TO_ISERDES[01]||ICE_TO_ISERDES_RT[01]), .ud(INC_DELAY||INC_TO_ISERDES[01]||INC_TO_ISERDES_RT[01]), .counter_value(TAP_01));
COUNT_TO_64 TAP_COUNTER_02(.clk(RXCLKDIV), .rst(IDLY_RESET||RESET), .count(ICE_DELAY||ICE_TO_ISERDES[02]||ICE_TO_ISERDES_RT[02]), .ud(INC_DELAY||INC_TO_ISERDES[02]||INC_TO_ISERDES_RT[02]), .counter_value(TAP_02));
COUNT_TO_64 TAP_COUNTER_03(.clk(RXCLKDIV), .rst(IDLY_RESET||RESET), .count(ICE_DELAY||ICE_TO_ISERDES[03]||ICE_TO_ISERDES_RT[03]), .ud(INC_DELAY||INC_TO_ISERDES[03]||INC_TO_ISERDES_RT[03]), .counter_value(TAP_03));
COUNT_TO_64 TAP_COUNTER_04(.clk(RXCLKDIV), .rst(IDLY_RESET||RESET), .count(ICE_DELAY||ICE_TO_ISERDES[04]||ICE_TO_ISERDES_RT[04]), .ud(INC_DELAY||INC_TO_ISERDES[04]||INC_TO_ISERDES_RT[04]), .counter_value(TAP_04));
COUNT_TO_64 TAP_COUNTER_05(.clk(RXCLKDIV), .rst(IDLY_RESET||RESET), .count(ICE_DELAY||ICE_TO_ISERDES[05]||ICE_TO_ISERDES_RT[05]), .ud(INC_DELAY||INC_TO_ISERDES[05]||INC_TO_ISERDES_RT[05]), .counter_value(TAP_05));
COUNT_TO_64 TAP_COUNTER_06(.clk(RXCLKDIV), .rst(IDLY_RESET||RESET), .count(ICE_DELAY||ICE_TO_ISERDES[06]||ICE_TO_ISERDES_RT[06]), .ud(INC_DELAY||INC_TO_ISERDES[06]||INC_TO_ISERDES_RT[06]), .counter_value(TAP_06));
COUNT_TO_64 TAP_COUNTER_07(.clk(RXCLKDIV), .rst(IDLY_RESET||RESET), .count(ICE_DELAY||ICE_TO_ISERDES[07]||ICE_TO_ISERDES_RT[07]), .ud(INC_DELAY||INC_TO_ISERDES[07]||INC_TO_ISERDES_RT[07]), .counter_value(TAP_07));
COUNT_TO_64 TAP_COUNTER_08(.clk(RXCLKDIV), .rst(IDLY_RESET||RESET), .count(ICE_DELAY||ICE_TO_ISERDES[08]||ICE_TO_ISERDES_RT[08]), .ud(INC_DELAY||INC_TO_ISERDES[08]||INC_TO_ISERDES_RT[08]), .counter_value(TAP_08));
COUNT_TO_64 TAP_COUNTER_09(.clk(RXCLKDIV), .rst(IDLY_RESET||RESET), .count(ICE_DELAY||ICE_TO_ISERDES[09]||ICE_TO_ISERDES_RT[09]), .ud(INC_DELAY||INC_TO_ISERDES[09]||INC_TO_ISERDES_RT[09]), .counter_value(TAP_09));
COUNT_TO_64 TAP_COUNTER_10(.clk(RXCLKDIV), .rst(IDLY_RESET||RESET), .count(ICE_DELAY||ICE_TO_ISERDES[10]||ICE_TO_ISERDES_RT[10]), .ud(INC_DELAY||INC_TO_ISERDES[10]||INC_TO_ISERDES_RT[10]), .counter_value(TAP_10));
COUNT_TO_64 TAP_COUNTER_11(.clk(RXCLKDIV), .rst(IDLY_RESET||RESET), .count(ICE_DELAY||ICE_TO_ISERDES[11]||ICE_TO_ISERDES_RT[11]), .ud(INC_DELAY||INC_TO_ISERDES[11]||INC_TO_ISERDES_RT[11]), .counter_value(TAP_11));
COUNT_TO_64 TAP_COUNTER_12(.clk(RXCLKDIV), .rst(IDLY_RESET||RESET), .count(ICE_DELAY||ICE_TO_ISERDES[12]||ICE_TO_ISERDES_RT[12]), .ud(INC_DELAY||INC_TO_ISERDES[12]||INC_TO_ISERDES_RT[12]), .counter_value(TAP_12));
COUNT_TO_64 TAP_COUNTER_13(.clk(RXCLKDIV), .rst(IDLY_RESET||RESET), .count(ICE_DELAY||ICE_TO_ISERDES[13]||ICE_TO_ISERDES_RT[13]), .ud(INC_DELAY||INC_TO_ISERDES[13]||INC_TO_ISERDES_RT[13]), .counter_value(TAP_13));
COUNT_TO_64 TAP_COUNTER_14(.clk(RXCLKDIV), .rst(IDLY_RESET||RESET), .count(ICE_DELAY||ICE_TO_ISERDES[14]||ICE_TO_ISERDES_RT[14]), .ud(INC_DELAY||INC_TO_ISERDES[14]||INC_TO_ISERDES_RT[14]), .counter_value(TAP_14));
COUNT_TO_64 TAP_COUNTER_15(.clk(RXCLKDIV), .rst(IDLY_RESET||RESET), .count(ICE_DELAY||ICE_TO_ISERDES[15]||ICE_TO_ISERDES_RT[15]), .ud(INC_DELAY||INC_TO_ISERDES[15]||INC_TO_ISERDES_RT[15]), .counter_value(TAP_15));


//CIRCUIT TO PRODUCE RESET DELAYED BY 20 CYCLES FOR BIT_ALIGN_MACHINE
integer		K;
always @(posedge RXCLKDIV)
	begin
	RESET_SM[0] <= RESET;
        for(K = 0; K <= 20 - 1; K = K + 1)
         begin
            RESET_SM[K+1] <= RESET_SM[K];
         end
	end

//DATA INPUT BUFFERS WITH DUAL OUTPUTS (ONE INVERTED AND ONE NOT INVERTED)