ddr_6to1_16chan_rt_rx.v3

FPGA之间的LVDS传输

			BITSLIP_TO_ISERDES <= {5'b00000, BITSLIP_FROM_MACHINE, 10'b0000000000};
			end
	
	4'b1011: 	begin
			DATA_TO_MACHINE <= DATA_FROM_ISERDES[71:66];
			INC_TO_ISERDES <= {4'b0000, INC_FROM_MACHINE, 11'b00000000000};
			ICE_TO_ISERDES <= {4'b0000, ICE_FROM_MACHINE, 11'b00000000000};
			BITSLIP_TO_ISERDES <= {4'b0000, BITSLIP_FROM_MACHINE, 11'b00000000000};
			end
	
	4'b1100: 	begin
			DATA_TO_MACHINE <= DATA_FROM_ISERDES[77:72];
			INC_TO_ISERDES <= {3'b000, INC_FROM_MACHINE, 12'b000000000000};
			ICE_TO_ISERDES <= {3'b000, ICE_FROM_MACHINE, 12'b000000000000};
			BITSLIP_TO_ISERDES <= {3'b000, BITSLIP_FROM_MACHINE, 12'b000000000000};
			end
	
	4'b1101: 	begin
			DATA_TO_MACHINE <= DATA_FROM_ISERDES[83:78];
			INC_TO_ISERDES <= {2'b00, INC_FROM_MACHINE, 13'b0000000000000};
			ICE_TO_ISERDES <= {2'b00, ICE_FROM_MACHINE, 13'b0000000000000};
			BITSLIP_TO_ISERDES <= {2'b00, BITSLIP_FROM_MACHINE, 13'b0000000000000};
			end
			
	4'b1110: 	begin
			DATA_TO_MACHINE <= DATA_FROM_ISERDES[89:84];
			INC_TO_ISERDES <= {1'b0, INC_FROM_MACHINE, 14'b00000000000000};
			ICE_TO_ISERDES <= {1'b0, ICE_FROM_MACHINE, 14'b00000000000000};
			BITSLIP_TO_ISERDES <= {1'b0, BITSLIP_FROM_MACHINE, 14'b00000000000000};
			end
			
	4'b1111: 	begin
			DATA_TO_MACHINE <= DATA_FROM_ISERDES[95:90];
			INC_TO_ISERDES <= {INC_FROM_MACHINE, 15'b000000000000000};
			ICE_TO_ISERDES <= {ICE_FROM_MACHINE, 15'b000000000000000};
			BITSLIP_TO_ISERDES <= {BITSLIP_FROM_MACHINE, 15'b000000000000000};
			end
endcase
end

//MACHINE THAT ALLOCATES BIT_ALIGN_MACHINE TO EACH OF THE 16 DATA CHANNELS, ONE AT A TIME	
RESOURCE_SHARING_CONTROL RESOURCE_SHARING_CONTROL_0
	(
	.CHAN_SEL(CHAN_SEL),
	.ALL_CHANNELS_ALIGNED(TRAINING_DONE),
	.DATA_ALIGNED(DATA_ALIGNED),
	.START_ALIGN(START_ALIGN),
	.CLK(RXCLKDIV),
	.RST(RESET),
	.REPEAT_PROC(1'b0)
	);	

//MACHINE THAT ADJUSTS DELAY OF A SINGLE DATA CHANNEL TO OPTIMIZE SAMPLING POINT 
BIT_ALIGN_MACHINE BIT_ALIGN_MACHINE_0
	(
	.RXCLKDIV(RXCLKDIV),
	.RXDATA(DATA_TO_MACHINE),
	.RST(RESET||RESET_SM[15]),
	.USE_BITSLIP(1'b1),
	.SAP(START_ALIGN),
	.INC(INC_FROM_MACHINE),
	.ICE(ICE_FROM_MACHINE),
	.BITSLIP(BITSLIP_FROM_MACHINE),
	.DATA_ALIGNED(DATA_ALIGNED)
	);

//MACHINE THAT ALLOCATES RT_WINDOW_MONITOR TO EACH OF THE 16 DATA CHANNELS, ONE AT A TIME	
RESOURCE_SHARING_CONTROL RESOURCE_SHARING_CONTROL_1
	(
	.CHAN_SEL(CHAN_SEL_RT),
	.ALL_CHANNELS_ALIGNED(),
	.DATA_ALIGNED(DATA_ALIGNED_RT),
	.START_ALIGN(START_ALIGN_RT),
	.CLK(RXCLKDIV),
	.RST(RESET),
	.REPEAT_PROC(1'b1)
	);	

//MACHINE THAT ADJUSTS DATA CHANNEL DELAYS IN REAL-TIME TO ACCOUNT FOR VT VARIATION
RT_WINDOW_MONITOR RT_WINDOW_MONITOR_0
	(
	.CLOCK(RXCLKDIV),
	.RESET(RESET),
	.TRAINING_DONE(TRAINING_DONE & RT_MANUAL_DISABLE),
	.START(START_ALIGN_RT),
	.DATA_MASTER(DATA_TO_RT),
	.DATA_MONITOR(MONITOR_TO_RT),
	.INC_MONITOR(INC_MONITOR),
	.ICE_MONITOR(ICE_MONITOR),
	.INC_DATABUS(INC_DATABUS),
	.ICE_DATABUS(ICE_DATABUS),
	.DATA_ALIGNED_RT(DATA_ALIGNED_RT)
	); 	

//CHANNEL SELECT LOGIC TO SHARE RT_WINDOW_MONITOR IN ROUND ROBIN FASHION
always @(posedge RXCLKDIV) begin
case (CHAN_SEL_RT)
	4'b0000: 	begin
			DATA_TO_RT <= DATA_FROM_ISERDES[5:0];
			MONITOR_TO_RT <= DATA_FROM_ISERDES_MON[5:0];
			INC_TO_ISERDES_RT <= {15'b000000000000000, INC_DATABUS};
			ICE_TO_ISERDES_RT <= {15'b000000000000000, ICE_DATABUS};
			INC_TO_MONITOR_RT <= {15'b000000000000000, INC_MONITOR};
			ICE_TO_MONITOR_RT <= {15'b000000000000000, ICE_MONITOR};
			end
	
	4'b0001: 	begin 
			DATA_TO_RT <= DATA_FROM_ISERDES[11:6];
			MONITOR_TO_RT <= DATA_FROM_ISERDES_MON[11:6];
			INC_TO_ISERDES_RT <= {14'b00000000000000, INC_DATABUS, 1'b0};
			ICE_TO_ISERDES_RT <= {14'b00000000000000, ICE_DATABUS, 1'b0};
			INC_TO_MONITOR_RT <= {14'b00000000000000, INC_MONITOR, 1'b0};
			ICE_TO_MONITOR_RT <= {14'b00000000000000, ICE_MONITOR, 1'b0};
			end
	
	4'b0010: 	begin
			DATA_TO_RT <= DATA_FROM_ISERDES[17:12];
			MONITOR_TO_RT <= DATA_FROM_ISERDES_MON[17:12];
			INC_TO_ISERDES_RT <= {13'b0000000000000, INC_DATABUS, 2'b00};
			ICE_TO_ISERDES_RT <= {13'b0000000000000, ICE_DATABUS, 2'b00};
			INC_TO_MONITOR_RT <= {13'b0000000000000, INC_MONITOR, 2'b00};
			ICE_TO_MONITOR_RT <= {13'b0000000000000, ICE_MONITOR, 2'b00};
			end
	
	4'b0011: 	begin
			DATA_TO_RT <= DATA_FROM_ISERDES[23:18];
			MONITOR_TO_RT <= DATA_FROM_ISERDES_MON[23:18];
			INC_TO_ISERDES_RT <= {12'b000000000000, INC_DATABUS, 3'b000};
			ICE_TO_ISERDES_RT <= {12'b000000000000, ICE_DATABUS, 3'b000};
			INC_TO_MONITOR_RT <= {12'b000000000000, INC_MONITOR, 3'b000};
			ICE_TO_MONITOR_RT <= {12'b000000000000, ICE_MONITOR, 3'b000};
			end
	
	4'b0100: 	begin
			DATA_TO_RT <= DATA_FROM_ISERDES[29:24];
			MONITOR_TO_RT <= DATA_FROM_ISERDES_MON[29:24];
			INC_TO_ISERDES_RT <= {11'b00000000000, INC_DATABUS, 4'b0000};
			ICE_TO_ISERDES_RT <= {11'b00000000000, ICE_DATABUS, 4'b0000};
			INC_TO_MONITOR_RT <= {11'b00000000000, INC_MONITOR, 4'b0000};
			ICE_TO_MONITOR_RT <= {11'b00000000000, ICE_MONITOR, 4'b0000};
			end
	
	4'b0101: 	begin
			DATA_TO_RT <= DATA_FROM_ISERDES[35:30];
			MONITOR_TO_RT <= DATA_FROM_ISERDES_MON[35:30];
			INC_TO_ISERDES_RT <= {10'b0000000000, INC_DATABUS, 5'b00000};
			ICE_TO_ISERDES_RT <= {10'b0000000000, ICE_DATABUS, 5'b00000};