ddr_6to1_16chan_rt_rx.v3

FPGA之间的LVDS传输

reg	[15:0]	INC_TO_ISERDES;
reg	[15:0]	ICE_TO_ISERDES_RT;
reg	[15:0]	INC_TO_ISERDES_RT;
reg	[15:0]	ICE_TO_MONITOR_RT;
reg	[15:0]	INC_TO_MONITOR_RT;
reg	[5:0]	DATA_TO_MACHINE;
reg	[5:0]	DATA_TO_RT;
reg	[5:0]	MONITOR_TO_RT;

integer		I;

assign 		INC_DELAY =	INC_PULSE;
assign 		ICE_DELAY = 	INC_PULSE || DEC_PULSE;
assign		TAP_CLK = 	6'h00;			//CLOCK DELAY IS NOT ADJUSTED IN THIS REFERENCE DESIGN

//IDELAYCTRL MODULE
IDELAYCTRL RX_IDELAYCTRL(.RDY(IDELAY_READY), .REFCLK(CLK200), .RST(IDELAYCTRL_RESET));


//SOURCE SYNCHRONOUS CLOCK INPUT
IBUFDS #(
	.DIFF_TERM("TRUE"),
	.IOSTANDARD("LVDS_25")
) SOURCE_SYNC_CLOCK_IN
	(
	.O(CLOCK_RX_BUF), 
	.I(CLOCK_RX_P), 
	.IB(CLOCK_RX_N)
	);


//IDELAY IN CLOCK PATH
IODELAY #(
	.IDELAY_TYPE("FIXED"),
	.IDELAY_VALUE(0),
	.ODELAY_VALUE(0),
	.REFCLK_FREQUENCY(200.00),
	.HIGH_PERFORMANCE_MODE("TRUE")
) ISERDES_CLOCK_RX
	(
	.DATAOUT(CLOCK_RX_ISERDES_OUT),
	.IDATAIN(CLOCK_RX_BUF),
	.ODATAIN(1'b0),
	.DATAIN(1'b0),
	.T(),
	.CE(1'b0),
	.INC(1'b0),
	.C(1'b0),
	.RST(RESET)
	);

//CLOCK BUFFER FOR SERIAL SIDE CLOCK	
BUFIO RX_CLK_BUFIO
	(
	.O(RXCLK), 
	.I(CLOCK_RX_ISERDES_OUT)
	);

//CLOCK BUFFER/DIVIDER FOR PARALLEL SIDE CLOCK
BUFR #(
	.BUFR_DIVIDE("3")
) RX_CLK_BUFR
	(
	.O(RXCLKDIV), 
	.CE(1'b1), 
	.CLR(1'b0), 
	.I(CLOCK_RX_ISERDES_OUT)
	);


//CHANNEL SELECT LOGIC TO SHARE ALIGNMENT MACHINE RESOURCES IN ROUND ROBIN FASHION
always @(posedge RXCLKDIV) begin
case (CHAN_SEL)
	4'b0000: 	begin
			DATA_TO_MACHINE <= DATA_FROM_ISERDES[5:0];
			INC_TO_ISERDES <= {15'b000000000000000, INC_FROM_MACHINE};
			ICE_TO_ISERDES <= {15'b000000000000000, ICE_FROM_MACHINE};
			BITSLIP_TO_ISERDES <= {15'b000000000000000, BITSLIP_FROM_MACHINE};
			end
	
	4'b0001: 	begin
			DATA_TO_MACHINE <= DATA_FROM_ISERDES[11:6];
			INC_TO_ISERDES <= {14'b00000000000000, INC_FROM_MACHINE, 1'b0};
			ICE_TO_ISERDES <= {14'b00000000000000, ICE_FROM_MACHINE, 1'b0};
			BITSLIP_TO_ISERDES <= {14'b00000000000000, BITSLIP_FROM_MACHINE, 1'b0};
			end
	
	4'b0010: 	begin
			DATA_TO_MACHINE <= DATA_FROM_ISERDES[17:12];
			INC_TO_ISERDES <= {13'b0000000000000, INC_FROM_MACHINE, 2'b00};
			ICE_TO_ISERDES <= {13'b0000000000000, ICE_FROM_MACHINE, 2'b00};
			BITSLIP_TO_ISERDES <= {13'b0000000000000, BITSLIP_FROM_MACHINE, 2'b00};
			end
	
	4'b0011: 	begin
			DATA_TO_MACHINE <= DATA_FROM_ISERDES[23:18];
			INC_TO_ISERDES <= {12'b000000000000, INC_FROM_MACHINE, 3'b000};
			ICE_TO_ISERDES <= {12'b000000000000, ICE_FROM_MACHINE, 3'b000};
			BITSLIP_TO_ISERDES <= {12'b000000000000, BITSLIP_FROM_MACHINE, 3'b000};
			end
	
	4'b0100: 	begin
			DATA_TO_MACHINE <= DATA_FROM_ISERDES[29:24];
			INC_TO_ISERDES <= {11'b00000000000, INC_FROM_MACHINE, 4'b0000};
			ICE_TO_ISERDES <= {11'b00000000000, ICE_FROM_MACHINE, 4'b0000};
			BITSLIP_TO_ISERDES <= {11'b00000000000, BITSLIP_FROM_MACHINE, 4'b0000};
			end
	
	4'b0101: 	begin
			DATA_TO_MACHINE <= DATA_FROM_ISERDES[35:30];
			INC_TO_ISERDES <= {10'b0000000000, INC_FROM_MACHINE, 5'b00000};
			ICE_TO_ISERDES <= {10'b0000000000, ICE_FROM_MACHINE, 5'b00000};
			BITSLIP_TO_ISERDES <= {10'b0000000000, BITSLIP_FROM_MACHINE, 5'b00000};
			end
	
	4'b0110: 	begin
			DATA_TO_MACHINE <= DATA_FROM_ISERDES[41:36];
			INC_TO_ISERDES <= {9'b000000000, INC_FROM_MACHINE, 6'b000000};
			ICE_TO_ISERDES <= {9'b000000000, ICE_FROM_MACHINE, 6'b000000};
			BITSLIP_TO_ISERDES <= {9'b000000000, BITSLIP_FROM_MACHINE, 6'b000000};
			end
	
	4'b0111: 	begin
			DATA_TO_MACHINE <= DATA_FROM_ISERDES[47:42];
			INC_TO_ISERDES <= {8'b00000000, INC_FROM_MACHINE, 7'b0000000};
			ICE_TO_ISERDES <= {8'b00000000, ICE_FROM_MACHINE, 7'b0000000};
			BITSLIP_TO_ISERDES <= {8'b00000000, BITSLIP_FROM_MACHINE, 7'b0000000};
			end
			
	4'b1000: 	begin
			DATA_TO_MACHINE <= DATA_FROM_ISERDES[53:48];
			INC_TO_ISERDES <= {7'b0000000, INC_FROM_MACHINE, 8'b00000000};
			ICE_TO_ISERDES <= {7'b0000000, ICE_FROM_MACHINE, 8'b00000000};
			BITSLIP_TO_ISERDES <= {7'b0000000, BITSLIP_FROM_MACHINE, 8'b00000000};
			end
			
	4'b1001: 	begin
			DATA_TO_MACHINE <= DATA_FROM_ISERDES[59:54];
			INC_TO_ISERDES <= {6'b000000, INC_FROM_MACHINE, 9'b000000000};
			ICE_TO_ISERDES <= {6'b000000, ICE_FROM_MACHINE, 9'b000000000};
			BITSLIP_TO_ISERDES <= {6'b000000, BITSLIP_FROM_MACHINE, 9'b000000000};
			end
	
	4'b1010: 	begin
			DATA_TO_MACHINE <= DATA_FROM_ISERDES[65:60];
			INC_TO_ISERDES <= {5'b00000, INC_FROM_MACHINE, 10'b0000000000};
			ICE_TO_ISERDES <= {5'b00000, ICE_FROM_MACHINE, 10'b0000000000};