ddr_6to1_16chan_rt_rx.v3

FPGA之间的LVDS传输

///////////////////////////////////////////////////////////////////////////////
//
//    File Name:  DDR_6TO1_16CHAN_RT_RX.v
//      Version:  1.0
//         Date:  08/07/06
//        Model:  XAPP860 LVDS Receiver Module
//
//      Company:  Xilinx, Inc.
//  Contributor:  APD Applications Group
//
//   Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
//                INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
//                PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
//                PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
//                ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
//                APPLICATION OR STANDARD, XILINX IS MAKING NO
//                REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
//                FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
//                RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
//                REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
//                EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
//                RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
//                INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//                REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
//                FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
//                OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
//                PURPOSE.
//
//                (c) Copyright 2006 Xilinx, Inc.
//                All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
// 
// Summary:
//
// The DDR_6TO1_16CHAN_RT_RX module contains all logic in the XAPP860 LVDS Receiver,
// including 16 channels of LVDS data, one channel of LVDS clock, an initial clock/data 
// alignment algorithm, a real-time clock/data alignment algorithm, a control circuit to share the alignment machines among
// all 16 data channels, and tap counters that keep track of the IDELAY tap
// setting of all data channels.
//  
//----------------------------------------------------------------

module DDR_6TO1_16CHAN_RT_RX
	(
	DATA_RX_P,
	DATA_RX_N,
	CLOCK_RX_P,
	CLOCK_RX_N,
	INC_PAD,
	DEC_PAD,
	DATA_FROM_ISERDES,
	RESET,
	IDLY_RESET,
	IDELAYCTRL_RESET,
	BITSLIP_PAD,
	CLK200,
	TAP_00,
	TAP_01,
	TAP_02,
	TAP_03,
	TAP_04,
	TAP_05,
	TAP_06,
	TAP_07,
	TAP_08,
	TAP_09,
	TAP_10,
	TAP_11,
	TAP_12,
	TAP_13,
	TAP_14,
	TAP_15,
	TAP_CLK,
	TRAINING_DONE,
	RXCLK,
	RXCLKDIV,
	IDELAY_READY,
	RT_MANUAL_DISABLE
	);

input	[15:0]	DATA_RX_P;		//SERIAL SIDE RX DATA (P)
input	[15:0]	DATA_RX_N;              //SERIAL SIDE RX DATA (N)
input		CLOCK_RX_P;		//FORWARDED CLOCK FROM TX (P)
input		CLOCK_RX_N;             //FORWARDED CLOCK FROM TX (N)
input		INC_PAD;		//MANUAL INCREMENT TO DATA DELAY
input		DEC_PAD;		//MANUAL DECREMENT TO DATA DELAY
input		RESET;			//RX DOMAIN RESET
input		IDLY_RESET;		//IDELAY TAP RESET
input		IDELAYCTRL_RESET;	//IDELAYCTRL CIRCUIT RESET
input		BITSLIP_PAD;		//MANUAL BITSLIP TO DATA
input		CLK200;			//200 MHZ REFERENCE CLOCK TO IDELAYCTRL				
input		RT_MANUAL_DISABLE;	//DISABLE REAL TIME WINDOW MONITORING

output	[95:0]	DATA_FROM_ISERDES;	//PARALLEL SIDE RX DATA
output	[5:0]	TAP_00;			//IDELAY TAP COUNT (0-63)
output	[5:0]	TAP_01;			//IDELAY TAP COUNT (0-63)
output	[5:0]	TAP_02;			//IDELAY TAP COUNT (0-63)
output	[5:0]	TAP_03;			//IDELAY TAP COUNT (0-63)
output	[5:0]	TAP_04;			//IDELAY TAP COUNT (0-63)
output	[5:0]	TAP_05;			//IDELAY TAP COUNT (0-63)
output	[5:0]	TAP_06;			//IDELAY TAP COUNT (0-63)
output	[5:0]	TAP_07;			//IDELAY TAP COUNT (0-63)
output	[5:0]	TAP_08;			//IDELAY TAP COUNT (0-63)
output	[5:0]	TAP_09;			//IDELAY TAP COUNT (0-63)
output	[5:0]	TAP_10;			//IDELAY TAP COUNT (0-63)
output	[5:0]	TAP_11;			//IDELAY TAP COUNT (0-63)
output	[5:0]	TAP_12;			//IDELAY TAP COUNT (0-63)
output	[5:0]	TAP_13;			//IDELAY TAP COUNT (0-63)
output	[5:0]	TAP_14;			//IDELAY TAP COUNT (0-63)
output	[5:0]	TAP_15;			//IDELAY TAP COUNT (0-63)
output	[5:0]	TAP_CLK;		//IDELAY TAP COUNT ON CLK CHANNEL (0-63)
output		TRAINING_DONE;		//ALIGNMENT OF ALL CHANNELS COMPLETE
output		RXCLK;			//FORWARDED CLOCK FROM TX (BUFIO OUTPUT)
output		RXCLKDIV;               //PARALLEL SIDE RX CLOCK (DIVIDED FROM RXCLK)
output		IDELAY_READY;		//FLAG INDICATING THAT IDELAYCTRL IS LOCKED

wire		CLOCK_RX_BUF;
wire	[15:0]	DATA_RX_BUF;
wire	[15:0]	DATA_RX_BUF_MON;
wire	[15:0]	DATA_RX_IDLY;
wire	[15:0]	DATA_RX_IDLY_MON;
wire	[95:0]	DATA_FROM_ISERDES_MON;
wire		CLOCK_RX_ISERDES_OUT;
wire		BITSLIP_FROM_MACHINE;
wire		ICE_FROM_MACHINE;
wire		INC_FROM_MACHINE;
wire		DATA_ALIGNED;
wire		DATA_ALIGNED_RT;
wire	[15:0]	SHIFT1;
wire	[15:0]	SHIFT2;
wire	[3:0]	CHAN_SEL;
wire	[3:0]	CHAN_SEL_RT;
wire		INC_MONITOR;
wire		ICE_MONITOR;
wire		INC_DATABUS;
wire		ICE_DATABUS;

reg	[3:0]	INC_CAPTURE;
reg	[3:0]	DEC_CAPTURE;
reg	[3:0]	BITSLIP_CAPTURE;
reg		INC_PULSE;
reg		DEC_PULSE;
reg		BITSLIP_PULSE;
reg	[20:0]	RESET_SM;
reg	[15:0]	BITSLIP_TO_ISERDES;
reg	[15:0]	ICE_TO_ISERDES;