test_vl.v

来自「FPGA之间的LVDS传输」· Verilog 代码 · 共 61 行

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:05:49 08/21/2008
// Design Name:   COUNT_TO_64
// Module Name:   E:/ISEworks/LVDS/LVDS_4to1/test_vl.v
// Project Name:  xapp860
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: COUNT_TO_64
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module test_vl;

	// Inputs
	reg clk;
	reg rst;
	reg count;
	reg ud;

	// Outputs
	wire [5:0] counter_value;

	// Instantiate the Unit Under Test (UUT)
	COUNT_TO_64 uut (
		.clk(clk), 
		.rst(rst), 
		.count(count), 
		.ud(ud), 
		.counter_value(counter_value)
	);

	initial begin
		// Initialize Inputs
		clk = 0;
		rst = 0;
		count = 0;
		ud = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
      
endmodule