test_vl.fdo

FPGA之间的LVDS传输

## NOTE:  Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Thu Aug 21 15:06:00 中国标准时间 2008
##
vlib work
vcom -explicit  -93 "COUNT_TO_64.vhd"
vlog +acc  "test_vl.v"
vlog +acc  "K:/Xilinx/10.1/ISE/verilog/src/glbl.v"
vsim -t 1ps   -L xilinxcorelib_ver -L unisims_ver -L unimacro_ver -L secureip -lib work test_vl glbl
do {test_vl_wave.fdo}
view wave
view structure
view signals
run 1000ns
do {test_vl.udo}