uut_tx_wrapper.vhd

FPGA之间的LVDS传输

--/////////////////////////////////////////////////////////////////////////////
--
--    File Name:  DDR_6TO1_16CHAN_RT_TX.vhd
--      Version:  1.0
--         Date:  08/07/06
--        Model:  XAPP860 LVDS Transmitter Module
--
--      Company:  Xilinx, Inc.
--  Contributor:  APD Applications Group
--
--   Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
--                INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
--                PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
--                PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
--                ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
--                APPLICATION OR STANDARD, XILINX IS MAKING NO
--                REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
--                FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
--                RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
--                REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
--                EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
--                RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
--                INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
--                REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
--                FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
--                OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--                PURPOSE.
--
--                (c) Copyright 2006 Xilinx, Inc.
--                All rights reserved.
--
--/////////////////////////////////////////////////////////////////////////////
-- 
-- Summary:
--
-- The DDR_6TO1_16CHAN_RT_TX module contains all components in the XAPP860 LVDS Transmitter,
-- including 16 channels of LVDS data, one channel of LVDS clock, and a multiplexer
-- that selects between a training pattern and user data.
-- 
------------------------------------------------------------------

----
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--

ENTITY uut_tx_wrapper IS
   PORT (
      DATA_TX_P               : OUT std_logic_vector(15 DOWNTO 0);   -- SERIAL SIDE TX DATA (P)
      DATA_TX_N               : OUT std_logic_vector(15 DOWNTO 0);   -- SERIAL SIDE TX DATA (N)
      CLOCK_TX_P              : OUT std_logic;   -- FORWARDED CLOCK TO RX (P)
      CLOCK_TX_N              : OUT std_logic;   -- FORWARDED CLOCK TO RX (N)
      TXCLK                   : IN std_logic;   -- SERIAL SIDE TX CLOCK
      TXCLKDIV                : IN std_logic;   -- PARALLEL SIDE TX CLOCK (DIVIDED FROM TXCLK)
      DATA_TO_OSERDES         : IN std_logic_vector(95 DOWNTO 0);   -- PARALLEL SIDE TX DATA
      RESET                   : IN std_logic;   -- TX DOMAIN RESET
      TRAINING_DONE           : IN std_logic);   -- FLAG FROM RECEIVER INDICATING ALIGNMENT
END uut_tx_wrapper;

ARCHITECTURE translated OF uut_tx_wrapper IS
	COMPONENT DDR_6TO1_16CHAN_RT_TX IS
   PORT (
      DATA_TX_P               : OUT std_logic_vector(15 DOWNTO 0);   -- SERIAL SIDE TX DATA (P)
      DATA_TX_N               : OUT std_logic_vector(15 DOWNTO 0);   -- SERIAL SIDE TX DATA (N)
      CLOCK_TX_P              : OUT std_logic;   -- FORWARDED CLOCK TO RX (P)
      CLOCK_TX_N              : OUT std_logic;   -- FORWARDED CLOCK TO RX (N)
      TXCLK                   : IN std_logic;   -- SERIAL SIDE TX CLOCK
      TXCLKDIV                : IN std_logic;   -- PARALLEL SIDE TX CLOCK (DIVIDED FROM TXCLK)
      DATA_TO_OSERDES         : IN std_logic_vector(95 DOWNTO 0);   -- PARALLEL SIDE TX DATA
      RESET                   : IN std_logic;   -- TX DOMAIN RESET
      TRAINING_DONE           : IN std_logic);   -- FLAG FROM RECEIVER INDICATING ALIGNMENT
END COMPONENT;

begin
	uutt : DDR_6TO1_16CHAN_RT_TX
		PORT MAP (
         DATA_TX_P => DATA_TX_P,
         DATA_TX_N => DATA_TX_N,
         CLOCK_TX_P => CLOCK_TX_P,
         CLOCK_TX_N => CLOCK_TX_N,
         TXCLK=> TXCLK,
         TXCLKDIV => TXCLKDIV,
         DATA_TO_OSERDES => DATA_TO_OSERDES,
         RESET => RESET,
         TRAINING_DONE => TRAINING_DONE); 
END translated;