ddr_6to1_16chan_rt_rx2.vhd

FPGA之间的LVDS传输

      Q3		: out std_logic;
      Q4		: out std_logic;
      Q5		: out std_logic;
      Q6		: out std_logic;
      SHIFTOUT1		: out std_logic;
      SHIFTOUT2		: out std_logic;
      BITSLIP		: in std_logic;
      CE1		: in std_logic;
      CE2		: in std_logic;
      CLK		: in std_logic;
      CLKDIV		: in std_logic;
      CLKB		: in std_logic;
      D			: in std_logic;
      OCLK		: in std_logic;
      RST		: in std_logic;
      SHIFTIN1		: in std_logic;
      SHIFTIN2		: in std_logic
    );
   end component;
 


   SIGNAL CLOCK_RX_BUF             :  std_logic;   
   SIGNAL DATA_RX_BUF              :  std_logic_vector(15 DOWNTO 0);   
   SIGNAL DATA_RX_BUF_MON          :  std_logic_vector(15 DOWNTO 0);   
   SIGNAL DATA_RX_IDLY             :  std_logic_vector(15 DOWNTO 0);   
   SIGNAL DATA_RX_IDLY_MON         :  std_logic_vector(15 DOWNTO 0);   
   SIGNAL DATA_FROM_ISERDES_MON    :  std_logic_vector(95 DOWNTO 0);   
   SIGNAL DATA_FROM_ISERDES_TEMP   :  std_logic_vector(95 DOWNTO 0);   
   SIGNAL CLOCK_RX_ISERDES_OUT     :  std_logic;   
   SIGNAL BITSLIP_FROM_MACHINE     :  std_logic;   
   SIGNAL ICE_FROM_MACHINE         :  std_logic;   
   SIGNAL INC_FROM_MACHINE         :  std_logic;   
   SIGNAL DATA_ALIGNED             :  std_logic;   
   SIGNAL DATA_ALIGNED_RT          :  std_logic;   
   SIGNAL SHIFT1                   :  std_logic_vector(15 DOWNTO 0);   
   SIGNAL SHIFT2                   :  std_logic_vector(15 DOWNTO 0);   
   SIGNAL CHAN_SEL                 :  std_logic_vector(3 DOWNTO 0);   
   SIGNAL CHAN_SEL_RT              :  std_logic_vector(3 DOWNTO 0);   
   SIGNAL INC_MONITOR              :  std_logic;   
   SIGNAL ICE_MONITOR              :  std_logic;   
   SIGNAL INC_DATABUS              :  std_logic;   
   SIGNAL ICE_DATABUS              :  std_logic;   
   SIGNAL INC_CAPTURE              :  std_logic_vector(3 DOWNTO 0);   
   SIGNAL DEC_CAPTURE              :  std_logic_vector(3 DOWNTO 0);   
   SIGNAL BITSLIP_CAPTURE          :  std_logic_vector(3 DOWNTO 0);   
   SIGNAL INC_PULSE                :  std_logic;   
   SIGNAL DEC_PULSE                :  std_logic;   
   SIGNAL BITSLIP_PULSE            :  std_logic;   
   SIGNAL RESET_SM                 :  std_logic_vector(20 DOWNTO 0);   
   SIGNAL BITSLIP_TO_ISERDES       :  std_logic_vector(15 DOWNTO 0);   
   SIGNAL ICE_TO_ISERDES           :  std_logic_vector(15 DOWNTO 0);   
   SIGNAL INC_TO_ISERDES           :  std_logic_vector(15 DOWNTO 0);   
   SIGNAL ICE_TO_ISERDES_RT        :  std_logic_vector(15 DOWNTO 0);   
   SIGNAL INC_TO_ISERDES_RT        :  std_logic_vector(15 DOWNTO 0);   
   SIGNAL ICE_TO_MONITOR_RT        :  std_logic_vector(15 DOWNTO 0);   
   SIGNAL INC_TO_MONITOR_RT        :  std_logic_vector(15 DOWNTO 0);   
   SIGNAL DATA_TO_MACHINE          :  std_logic_vector(5 DOWNTO 0);   
   SIGNAL DATA_TO_RT               :  std_logic_vector(5 DOWNTO 0);   
   SIGNAL MONITOR_TO_RT            :  std_logic_vector(5 DOWNTO 0);   
   SIGNAL I                        :  integer;   


   SIGNAL ICE_DELAY                :  std_logic;   
   SIGNAL INC_DELAY                :  std_logic;   
   SIGNAL START_ALIGN              :  std_logic;   
   SIGNAL START_ALIGN_RT           :  std_logic;   
   SIGNAL RXCLKDIV_TEMP, RXCLK_TEMP       :  std_logic;   
   SIGNAL BIT_ALIGN_MACHINE_RESET  :  std_logic;

   SIGNAL RT_WINDOW_MONITOR_TRAINING:  std_logic;
   SIGNAL K                        :  integer;   
   SIGNAL TRAINING_DONE_TEMP       :  std_logic;
   SIGNAL RX_MON_RESET       :  std_logic;

SIGNAL  TEMP_TAP_RST_00, TEMP_TAP_RST_01, TEMP_TAP_RST_02,
           TEMP_TAP_RST_03, TEMP_TAP_RST_04, TEMP_TAP_RST_05,
           TEMP_TAP_RST_06, TEMP_TAP_RST_07, TEMP_TAP_RST_08,
           TEMP_TAP_RST_09, TEMP_TAP_RST_10, TEMP_TAP_RST_11,
           TEMP_TAP_RST_12, TEMP_TAP_RST_13, TEMP_TAP_RST_14, 
           TEMP_TAP_RST_15         :  std_logic;
   SIGNAL  TEMP_TAP_CNT_00, TEMP_TAP_CNT_01, TEMP_TAP_CNT_02,
           TEMP_TAP_CNT_03, TEMP_TAP_CNT_04, TEMP_TAP_CNT_05,
           TEMP_TAP_CNT_06, TEMP_TAP_CNT_07, TEMP_TAP_CNT_08,
           TEMP_TAP_CNT_09, TEMP_TAP_CNT_10, TEMP_TAP_CNT_11,
           TEMP_TAP_CNT_12, TEMP_TAP_CNT_13, TEMP_TAP_CNT_14,
           TEMP_TAP_CNT_15         :  std_logic;
   SIGNAL  TEMP_TAP_UD_00, TEMP_TAP_UD_01, TEMP_TAP_UD_02,
           TEMP_TAP_UD_03, TEMP_TAP_UD_04, TEMP_TAP_UD_05,
           TEMP_TAP_UD_06, TEMP_TAP_UD_07, TEMP_TAP_UD_08,
           TEMP_TAP_UD_09, TEMP_TAP_UD_10, TEMP_TAP_UD_11,
           TEMP_TAP_UD_12, TEMP_TAP_UD_13, TEMP_TAP_UD_14,
           TEMP_TAP_UD_15          :  std_logic;
   
SIGNAL  RX_DATA_CE_00, RX_DATA_CE_01, RX_DATA_CE_02, RX_DATA_CE_03 :  std_logic;
SIGNAL  RX_DATA_CE_04, RX_DATA_CE_05, RX_DATA_CE_06, RX_DATA_CE_07 :  std_logic;
SIGNAL  RX_DATA_CE_08, RX_DATA_CE_09, RX_DATA_CE_10, RX_DATA_CE_11 :  std_logic;
SIGNAL  RX_DATA_CE_12, RX_DATA_CE_13, RX_DATA_CE_14, RX_DATA_CE_15 :  std_logic;

SIGNAL  RX_DATA_INC_00, RX_DATA_INC_01, RX_DATA_INC_02, RX_DATA_INC_03 :  std_logic;
SIGNAL  RX_DATA_INC_04, RX_DATA_INC_05, RX_DATA_INC_06, RX_DATA_INC_07 :  std_logic;
SIGNAL  RX_DATA_INC_08, RX_DATA_INC_09, RX_DATA_INC_10, RX_DATA_INC_11 :  std_logic;
SIGNAL  RX_DATA_INC_12, RX_DATA_INC_13, RX_DATA_INC_14, RX_DATA_INC_15 :  std_logic;

SIGNAL   RX_DATA_RESET :  std_logic;
SIGNAL BITSLIP_00, BITSLIP_01, BITSLIP_02, BITSLIP_03 :  std_logic;
SIGNAL BITSLIP_04, BITSLIP_05, BITSLIP_06, BITSLIP_07 :  std_logic;
SIGNAL BITSLIP_08, BITSLIP_09, BITSLIP_10, BITSLIP_11 :  std_logic;
SIGNAL BITSLIP_12, BITSLIP_13, BITSLIP_14, BITSLIP_15 :  std_logic;

SIGNAL MON_BITSLIP_00, MON_BITSLIP_01, MON_BITSLIP_02, MON_BITSLIP_03 :  std_logic;
SIGNAL MON_BITSLIP_04, MON_BITSLIP_05, MON_BITSLIP_06, MON_BITSLIP_07 :  std_logic;
SIGNAL MON_BITSLIP_08, MON_BITSLIP_09, MON_BITSLIP_10, MON_BITSLIP_11 :  std_logic;
SIGNAL MON_BITSLIP_12, MON_BITSLIP_13, MON_BITSLIP_14, MON_BITSLIP_15 :  std_logic;


SIGNAL RX_MON_CE_00, RX_MON_CE_01, RX_MON_CE_02, RX_MON_CE_03  :  std_logic;
SIGNAL RX_MON_CE_04, RX_MON_CE_05, RX_MON_CE_06, RX_MON_CE_07  :  std_logic;
SIGNAL RX_MON_CE_08, RX_MON_CE_09, RX_MON_CE_10, RX_MON_CE_11  :  std_logic;
SIGNAL RX_MON_CE_12, RX_MON_CE_13, RX_MON_CE_14, RX_MON_CE_15  :  std_logic;

SIGNAL RX_MON_INC_00, RX_MON_INC_01, RX_MON_INC_02, RX_MON_INC_03  :  std_logic;
SIGNAL RX_MON_INC_04, RX_MON_INC_05, RX_MON_INC_06, RX_MON_INC_07  :  std_logic;
SIGNAL RX_MON_INC_08, RX_MON_INC_09, RX_MON_INC_10, RX_MON_INC_11  :  std_logic;
SIGNAL RX_MON_INC_12, RX_MON_INC_13, RX_MON_INC_14, RX_MON_INC_15  :  std_logic;


BEGIN
   --DATA_FROM_ISERDES <= DATA_FROM_ISERDES_TEMP;
   RXCLK <= RXCLK_TEMP;
   --TRAINING_DONE <= TRAINING_DONE_TEMP;   
	--INC_DELAY <= INC_PULSE ;
   --ICE_DELAY <= INC_PULSE OR DEC_PULSE ;
-- OBUF_i : OBUF
--	 PORT MAP (
--         I => RXCLK_TEMP,
--         O => RXCLK); 
--   
--RXCLKDIV <= RXCLKDIV_TEMP;

   --IDELAYCTRL MODULE

--   RX_IDELAYCTRL : IDELAYCTRL 
--      PORT MAP (
--         RDY => IDELAY_READY,
--         REFCLK => CLK200,
--         RST => IDELAYCTRL_RESET);   
   
   
   --SOURCE SYNCHRONOUS CLOCK INPUT

   SOURCE_SYNC_CLOCK_IN : IBUFDS 
      GENERIC MAP(
         DIFF_TERM => TRUE, IOSTANDARD =>"LVDS_25") 
      PORT MAP (
         O => CLOCK_RX_BUF,
         I => CLOCK_RX_P,
         IB => CLOCK_RX_N);   
   
   
--   --IDELAY IN CLOCK PATH
--
--   ISERDES_CLOCK_RX : IODELAY 
--      GENERIC MAP(
--         IDELAY_TYPE => "FIXED", IDELAY_VALUE => 0, 
--         ODELAY_VALUE => 0, REFCLK_FREQUENCY => 200.00,  
--        HIGH_PERFORMANCE_MODE => "TRUE") 
--      PORT MAP (
--         DATAOUT => CLOCK_RX_ISERDES_OUT,
--         IDATAIN => CLOCK_RX_BUF,
--         ODATAIN => '0',
--         DATAIN => '0',
--         T => '1',
--         CE => '0',
--         INC => '0',
--         C => '0',
--         RST => RESET);   
--   
   
   --CLOCK BUFFER FOR SERIAL SIDE CLOCK	

   RX_CLK_BUFIO : BUFIO 
      PORT MAP (
         O => RXCLK_TEMP,
         I => CLOCK_RX_BUF);   
   
   

END translated;