ddr_6to1_16chan_rt_rx2.vhd

FPGA之间的LVDS传输

--/////////////////////////////////////////////////////////////////////////////
--
--    File Name:  DDR_6TO1_16CHAN_RT_RX.vhd
--      Version:  1.0
--         Date:  08/07/06
--        Model:  XAPP860 LVDS Receiver Module
--
--      Company:  Xilinx, Inc.
--  Contributor:  APD Applications Group
--
--   Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
--                INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
--                PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
--                PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
--                ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
--                APPLICATION OR STANDARD, XILINX IS MAKING NO
--                REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
--                FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
--                RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
--                REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
--                EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
--                RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
--                INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
--                REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
--                FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
--                OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
--                PURPOSE.
--
--                (c) Copyright 2006 Xilinx, Inc.
--                All rights reserved.
--
--/////////////////////////////////////////////////////////////////////////////
-- 
-- Summary:
--
-- The DDR_6TO1_16CHAN_RT_RX module contains all logic in the XAPP860 LVDS Receiver,
-- including 16 channels of LVDS data, one channel of LVDS clock, an initial clock/data 
-- alignment algorithm, a real-time clock/data alignment algorithm, a control circuit to share the alignment machines among
-- all 16 data channels, and tap counters that keep track of the IDELAY tap
-- setting of all data channels.
--  
------------------------------------------------------------------

----
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--

ENTITY DDR_6TO1_16CHAN_RT_RX IS
   PORT (
      DATA_RX_P   : IN std_logic_vector(15 DOWNTO 0); -- SERIAL SIDE RX DATA (P)
      DATA_RX_N   : IN std_logic_vector(15 DOWNTO 0); -- SERIAL SIDE RX DATA (N)
      CLOCK_RX_P  : IN std_logic;   -- FORWARDED CLOCK FROM TX (P)
      CLOCK_RX_N  : IN std_logic;   -- FORWARDED CLOCK FROM TX (N)
      INC_PAD     : IN std_logic;   -- MANUAL INCREMENT TO DATA DELAY
      DEC_PAD     : IN std_logic;   -- MANUAL DECREMENT TO DATA DELAY
      DATA_FROM_ISERDES       : OUT std_logic_vector(95 DOWNTO 0);   
                                 -- PARALLEL SIDE RX DATA
      RESET           : IN std_logic;   -- RX DOMAIN RESET
      IDLY_RESET        : IN std_logic;   -- IDELAY TAP RESET
      IDELAYCTRL_RESET  : IN std_logic;   -- IDELAYCTRL CIRCUIT RESET
      BITSLIP_PAD       : IN std_logic;   -- MANUAL BITSLIP TO DATA
      CLK200            : IN std_logic; -- 200 MHZ REFERENCE CLOCK TO IDELAYCTRL				
      TAP_00     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_01     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_02     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_03     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_04     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_05     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_06     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_07     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_08     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_09     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_10     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_11     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_12     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_13     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_14     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_15     : OUT std_logic_vector(5 DOWNTO 0); -- IDELAY TAP COUNT (0-63)
      TAP_CLK    : OUT std_logic_vector(5 DOWNTO 0); 
                            -- IDELAY TAP COUNT ON CLK CHANNEL (0-63)
      TRAINING_DONE  : OUT std_logic;   -- ALIGNMENT OF ALL CHANNELS COMPLETE
      RXCLK          : OUT std_logic;   
                                 -- FORWARDED CLOCK FROM TX (BUFIO OUTPUT)
      RXCLKDIV       : OUT std_logic;   
                                 -- PARALLEL SIDE RX CLOCK (DIVIDED FROM RXCLK)
      IDELAY_READY   : OUT std_logic;   
                                 -- FLAG INDICATING THAT IDELAYCTRL IS LOCKED
      RT_MANUAL_DISABLE       : IN std_logic);   
                                 -- DISABLE REAL TIME WINDOW MONITORING
END DDR_6TO1_16CHAN_RT_RX;

ARCHITECTURE translated OF DDR_6TO1_16CHAN_RT_RX IS

   COMPONENT COUNT_TO_64
      PORT (
         clk                     : IN  std_logic;
         rst                     : IN  std_logic;
         count                   : IN  std_logic;
         ud                      : IN  std_logic;
         counter_value           : OUT std_logic_vector(5 DOWNTO 0));
   END COMPONENT;

   COMPONENT BIT_ALIGN_MACHINE
      PORT (
         RXCLKDIV                : IN  std_logic;
         RXDATA                  : IN  std_logic_vector(5 DOWNTO 0);
         RST                     : IN  std_logic;
         USE_BITSLIP             : IN  std_logic;
         SAP                     : IN  std_logic;
         INC                     : OUT std_logic;
         ICE                     : OUT std_logic;
         BITSLIP                 : OUT std_logic;
         DATA_ALIGNED            : OUT std_logic);
   END COMPONENT;

   COMPONENT RESOURCE_SHARING_CONTROL
      PORT (
         CHAN_SEL                : OUT std_logic_vector(3 DOWNTO 0);
         ALL_CHANNELS_ALIGNED    : OUT std_logic;
         DATA_ALIGNED            : IN  std_logic;
         START_ALIGN             : OUT std_logic;
         CLK                     : IN  std_logic;
         RST                     : IN  std_logic;
         REPEAT_PROC             : IN  std_logic);
   END COMPONENT;

   COMPONENT RT_WINDOW_MONITOR
      PORT (
         CLOCK                   : IN  std_logic;
         RESET                   : IN  std_logic;
         TRAINING_DONE           : IN  std_logic;
         START                   : IN  std_logic;
         DATA_MASTER             : IN  std_logic_vector(5 DOWNTO 0);
         DATA_MONITOR            : IN  std_logic_vector(5 DOWNTO 0);
         INC_MONITOR             : OUT std_logic;
         ICE_MONITOR             : OUT std_logic;
         INC_DATABUS             : OUT std_logic;
         ICE_DATABUS             : OUT std_logic;
         DATA_ALIGNED_RT         : OUT std_logic);
   END COMPONENT;


  component IODELAY 
  generic(
      IDELAY_TYPE	: string	:= "DEFAULT";
      IDELAY_VALUE	: integer	:= 0;
      ODELAY_VALUE	: integer	:= 0;
      REFCLK_FREQUENCY	: real		:= 200.0;
      HIGH_PERFORMANCE_MODE	: string		:= "TRUE"
      );
  port(
      DATAOUT	: out std_logic;

      C		: in  std_logic;
      CE	: in  std_logic;
      DATAIN	: in  std_logic;
      IDATAIN	: in  std_logic;
      INC	: in  std_logic;
      ODATAIN	: in  std_logic;
      RST	: in  std_logic;
      T		: in  std_logic
      );
end component;


    component ISERDES_NODELAY 
   generic(
      BITSLIP_ENABLE	: boolean	:= false;
      DATA_RATE		: string	:= "DDR";
      DATA_WIDTH	: integer	:= 4;
      INIT_Q1		: std_logic		:= '0';
      INIT_Q2		: std_logic		:= '0';
      INIT_Q3		: std_logic		:= '0';
      INIT_Q4		: std_logic		:= '0';
      INTERFACE_TYPE	: string	:= "MEMORY";
      NUM_CE		: integer	:= 2;
      SERDES_MODE	: string	:= "MASTER"
      );
  port(
      Q1		: out std_logic;
      Q2		: out std_logic;