bit_align_machine.vhd

FPGA之间的LVDS传输

                     IF (RXDATA_PREV /= RXDATA) THEN
                        NEXT_STATE <= "01111";    
                     ELSE
                        NEXT_STATE <= "01011";    
                     END IF;
                  END IF;
         WHEN "01110" =>
                  --DATA IS STABLE AFTER FINDING 1ST TRANS, 
                  --COUNT 1 TO INCLUDE LAST INC
                  
                  NEXT_STATE <= "01001";    
         WHEN "01001" =>
                  --INC ONCE TO LOOK FOR 2ND TRANS
                  
                  NEXT_STATE <= "00011";    
         WHEN "00011" =>
                  --WAIT 8 CYCLES, COMPARE RXDATA WITH PREVIOUS DATA
                  
                  IF (COUNT_VALUE_SAMPLE < "0000111") THEN
                     NEXT_STATE <= "00011";    
                  ELSE
                     IF (RXDATA_PREV /= RXDATA) THEN
                        NEXT_STATE <= "10010";    
                     ELSE
                        NEXT_STATE <= "01001";    
                     END IF;
                  END IF;
         WHEN "10010" =>
                  --IDLE (NEEDED FOR COUNTER RESET BEFORE NEXT STATE)
                  
                  NEXT_STATE <= "01010";    
         WHEN "01010" =>
                  --DECREMENT TO MIDDLE OF DATA EYE
                  
                  IF (COUNT_VALUE_SAMPLE < HALF_DATA_EYE - "0000001") 
                  THEN
                     NEXT_STATE <= "01010";    
                  ELSE
                     NEXT_STATE <= "00101";    
                  END IF;
         WHEN "00101" =>
                  --SAMPLE PATTERN 16 TIMES TO SEE IF WORD ALIGNMENT NEEDED
                  
                  IF (USE_BITSLIP = '0') THEN
                     NEXT_STATE <= "00111";    
                  ELSE
                     IF (COUNT_VALUE < "0001111") THEN
                        NEXT_STATE <= "00101";    
                     ELSE
                        IF (RXDATA = CHECK_PATTERN) THEN
                           NEXT_STATE <= "00111";    
                        ELSE
                           --if(COUNT_VALUE == 7'h0F)
                           
                           NEXT_STATE <= "00110";    
                        END IF;
                     END IF;
                  END IF;
         WHEN "00110" =>
                  --INITIATE 1 BITSLIP
                  
                  NEXT_STATE <= "00101";    
         WHEN "00111" =>
                  IF (SAP = '0') THEN
                     --TRAINING COMPLETE FOR THIS CHANNEL
                     
                     NEXT_STATE <= "00111";    
                  ELSE
                     NEXT_STATE <= "00000";    
                  END IF;
         WHEN OTHERS  =>
                  NEXT_STATE <= "00000";    
         
      END CASE;
   END PROCESS;

   --OUTPUT LOGIC
   
   PROCESS (CURRENT_STATE)
   BEGIN
      CASE CURRENT_STATE IS
         WHEN "00000" =>
                  --RST STATE
                  
                  INC  <= '0';    
                  ICE  <= '0';    
                  COUNT  <= '0';    
                  UD  <= '0';    
                  STORE  <= '0';    
                  STORE_DATA_PREV  <= '1';    
                  BITSLIP  <= '0';    
                  COUNT_SAMPLE  <= '0';    
                  UD_SAMPLE  <= '0';    
         WHEN "00001" =>
                  --INITIAL STATE, SAMPLE TRAINING BIT
                  
                  INC  <= '0';    
                  ICE  <= '0';    
                  COUNT  <= '0';    
                  UD  <= '0';    
                  STORE  <= '0';    
                  STORE_DATA_PREV  <= '1';    
                  BITSLIP  <= '0';    
                  COUNT_SAMPLE  <= '0';    
                  UD_SAMPLE  <= '0';    
         WHEN "01000" =>
                  --CHECK SAMPLE TO SEE IF IT IS ON A TRANSITION
                  
                  INC  <= '0';    
                  ICE  <= '0';    
                  COUNT  <= '0';    
                  UD  <= '1';    
                  STORE  <= '0';    
                  STORE_DATA_PREV  <= '1';    
                  BITSLIP  <= '0';    
                  COUNT_SAMPLE  <= '1';    
                  UD_SAMPLE  <= '1';    
         WHEN "01111" =>
                  --IF SAMPLED POINT IS TRANSITION, EDGE IS FOUND, SO INC DELAY TO EXIT TRANSITION
                  
                  INC  <= '1';    
                  ICE  <= '1';    
                  COUNT  <= '0';    
                  UD  <= '1';    
                  STORE  <= '0';    
                  STORE_DATA_PREV  <= '1';    
                  BITSLIP  <= '0';    
                  COUNT_SAMPLE  <= '0';    
                  UD_SAMPLE  <= '0';    
         WHEN "01101" =>
                  --WAIT 16 CYCLES WHILE APPLYING BITSLIP TO FIND CHECK_PATTERN
                  
                  INC  <= '0';    
                  ICE  <= '0';    
                  COUNT  <= '0';    
                  UD  <= '1';    
                  STORE  <= '0';    
                  STORE_DATA_PREV  <= '1';    
                  BITSLIP  <= '1';    
                  COUNT_SAMPLE  <= '1';    
                  UD_SAMPLE  <= '1';    
         WHEN "01100" =>
                  --IDLE (NEEDED FOR COUNTER RESET BEFORE NEXT STATE)
                  
                  INC  <= '0';    
                  ICE  <= '0';    
                  COUNT  <= '0';    
                  UD  <= '1';    
                  STORE  <= '0';    
                  STORE_DATA_PREV  <= '1';    
                  BITSLIP  <= '0';    
                  COUNT_SAMPLE  <= '0';    
                  UD_SAMPLE  <= '0';    
         WHEN "10000" =>
                  --IDLE (NEEDED FOR STABILIZATION)
                  
                  INC  <= '0';    
                  ICE  <= '0';    
                  COUNT  <= '0';    
                  UD  <= '1';    
                  STORE  <= '0';    
                  STORE_DATA_PREV  <= '1';    
                  BITSLIP  <= '0';    
                  COUNT_SAMPLE  <= '0';    
                  UD_SAMPLE  <= '0';    
         WHEN "00010" =>
                  --CHECK SAMPLE AGAIN TO SEE IF WE HAVE EXITED TRANSITION
                  
                  INC  <= '0';    
                  ICE  <= '0';    
                  COUNT  <= '0';    
                  UD  <= '1';    
                  STORE  <= '0';    
                  STORE_DATA_PREV  <= '1';    
                  BITSLIP  <= '0';    
                  COUNT_SAMPLE  <= '1';    
                  UD_SAMPLE  <= '1';    
         WHEN "01011" =>
                  --INITIAL STATE WAS STABLE, SO INC ONCE TO SEARCH FOR TRANS
                  
                  INC  <= '1';    
                  ICE  <= '1';    
                  COUNT  <= '0';    
                  UD  <= '0';    
                  STORE  <= '0';    
                  STORE_DATA_PREV  <= '1';    
                  BITSLIP  <= '0';    
                  COUNT_SAMPLE  <= '0';    
                  UD_SAMPLE  <= '0';    
         WHEN "00100" =>
                  --WAIT 8 CYCLES, COMPARE RXDATA WITH PREVIOUS DATA
                  
                  INC  <= '0';    
                  ICE  <= '0';    
                  COUNT  <= '0';    
                  UD  <= '0';    
                  STORE  <= '0';    
                  STORE_DATA_PREV  <= '0';    
                  BITSLIP  <= '0';    
                  COUNT_SAMPLE  <= '1';    
                  UD_SAMPLE  <= '1';    
         WHEN "01110" =>
                  --DATA IS STABLE AFTER FINDING 1ST TRANS, COUNT 1 TO INCLUDE LAST INC
                  
                  INC  <= '0';    
                  ICE  <= '0';    
                  COUNT  <= '1';    
                  UD  <= '1';    
                  STORE  <= '0';    
                  STORE_DATA_PREV  <= '1';    
                  BITSLIP  <= '0';    
                  COUNT_SAMPLE  <= '0';    
                  UD_SAMPLE  <= '0';    
         WHEN "01001" =>
                  --INC ONCE TO LOOK FOR 2ND TRANS
                  
                  INC  <= '1';    
                  ICE  <= '1';    
                  COUNT  <= '1';    
                  UD  <= '1';    
                  STORE  <= '0';    
                  STORE_DATA_PREV  <= '1';    
                  BITSLIP  <= '0';    
                  COUNT_SAMPLE  <= '0';    
                  UD_SAMPLE  <= '0';    
         WHEN "00011" =>
                  --WAIT 8 CYCLES, COMPARE RXDATA WITH PREVIOUS DATA
                  
                  INC  <= '0';    
                  ICE  <= '0';    
                  COUNT  <= '0';    
                  UD  <= '1';    
                  STORE  <= '1';    
                  STORE_DATA_PREV  <= '0';    
                  BITSLIP  <= '0';    
                  COUNT_SAMPLE  <= '1';    
                  UD_SAMPLE  <= '1';    
         WHEN "10010" =>
                  --IDLE (NEEDED FOR COUNTER RESET BEFORE NEXT STATE)
                  
                  INC  <= '0';    
                  ICE  <= '0';    
                  COUNT  <= '0';    
                  UD  <= '0';    
                  STORE  <= '0';    
                  STORE_DATA_PREV  <= '1';    
                  BITSLIP  <= '0';    
                  COUNT_SAMPLE  <= '0';    
                  UD_SAMPLE  <= '0';    
         WHEN "01010" =>
                  --DECREMENT TO CENTER OF DATA EYE
                  
                  INC  <= '0';    
                  ICE  <= '1';    
                  COUNT  <= '0';    
                  UD  <= '0';    
                  STORE  <= '0';    
                  STORE_DATA_PREV  <= '1';    
                  BITSLIP  <= '0';    
                  COUNT_SAMPLE  <= '1';    
                  UD_SAMPLE  <= '1';    
         WHEN "00101" =>
                  --SAMPLE PATTERN 16 TIMES TO SEE IF WORD ALIGNMENT NEEDED
                  
                  INC  <= '0';    
                  ICE  <= '0';    
                  COUNT  <= '1';    
                  UD  <= '1';    
                  STORE  <= '0';    
                  STORE_DATA_PREV  <= '1';    
                  BITSLIP  <= '0';    
                  COUNT_SAMPLE  <= '0';    
                  UD_SAMPLE  <= '0';    
         WHEN "00110" =>
                  --INITIATE 1 BITSLIP
                  
                  INC  <= '0';    
                  ICE  <= '0';    
                  COUNT  <= '0';    
                  UD  <= '0';    
                  STORE  <= '0';    
                  STORE_DATA_PREV  <= '1';    
                  BITSLIP  <= '1';    
                  COUNT_SAMPLE  <= '0';    
                  UD_SAMPLE  <= '0';    
         WHEN "00111" =>
                  --TRAINING COMPLETE ON THIS CHANNEL
                  
                  INC  <= '0';    
                  ICE  <= '0';    
                  COUNT  <= '0';    
                  UD  <= '0';    
                  STORE  <= '0';    
                  STORE_DATA_PREV  <= '1';    
                  BITSLIP  <= '0';    
                  COUNT_SAMPLE  <= '0';    
                  UD_SAMPLE  <= '0';    
         WHEN OTHERS  =>
                  INC  <= '0';    
                  ICE  <= '0';    
                  COUNT  <= '0';    
                  UD  <= '0';    
                  STORE  <= '0';    
                  STORE_DATA_PREV <= '1';    
                  BITSLIP  <= '0';    
                  COUNT_SAMPLE  <= '0';    
                  UD_SAMPLE  <= '0';    
         
      END CASE;
   END PROCESS;

END translated;