lvds_tx_rx_merge_map.mrp

FPGA之间的LVDS传输

   pin. With NUM_CE set 1 the CE2 input pin is being ignored.

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs.
INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range:
   0.000 to 85.000 Celsius)
INFO:Pack:1720 - Initializing voltage to 0.950 Volts. (default - Range: 0.950 to
   1.050 Volts)
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
INFO:Pack:1650 - Map created a placed design.

Section 4 - Removed Logic Summary
---------------------------------
  15 block(s) removed
   6 block(s) optimized away
  11 signal(s) removed

Section 5 - Removed Logic
-------------------------

The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections.  If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented.  This
indentation will be repeated as a chain of related logic is removed.

To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).

The signal "uut_tx/U_FIFO/full" is sourceless and has been removed.
The signal "uut_tx/U_FIFO/empty" is sourceless and has been removed.
The signal "uut_rx/U_FIFO/full" is sourceless and has been removed.
The signal "uut_rx/U_FIFO/empty" is sourceless and has been removed.
The signal "uut_rx/U_FIFO/almost_full" is sourceless and has been removed.
The signal
"uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_not0001" is
sourceless and has been removed.
 Sourceless block
"uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i" (FF) removed.
The signal
"uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000" is
sourceless and has been removed.
The signal "uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/wr_rst_d1" is
sourceless and has been removed.
 Sourceless block
"uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_not00011" (ROM)
removed.
 Sourceless block
"uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000144"
(ROM) removed.
The signal
"uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux00008" is
sourceless and has been removed.
The signal
"uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000035" is
sourceless and has been removed.
The signal
"uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000112" is
sourceless and has been removed.
Unused block "uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i" (FF)
removed.
Unused block
"uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux0000112"
(ROM) removed.
Unused block
"uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux000035" (ROM)
removed.
Unused block
"uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_almost_full_i_mux00008" (ROM)
removed.
Unused block "uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i" (FF)
removed.
Unused block "uut_rx/U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/wr_rst_d1" (FF)
removed.
Unused block "uut_rx/U_FIFO/GND" (ZERO) removed.
Unused block "uut_rx/U_FIFO/VCC" (ONE) removed.
Unused block "uut_tx/U_FIFO/BU2/U0/grf.rf/gl0.rd/gras.rsts/ram_empty_i" (FF)
removed.
Unused block "uut_tx/U_FIFO/BU2/U0/grf.rf/gl0.wr/gwas.wsts/ram_full_i" (FF)
removed.
Unused block "uut_tx/U_FIFO/GND" (ZERO) removed.
Unused block "uut_tx/U_FIFO/VCC" (ONE) removed.

Optimized Block(s):
TYPE 		BLOCK
GND 		XST_GND
VCC 		XST_VCC
GND 		uut_rx/U_FIFO/BU2/XST_GND
VCC 		uut_rx/U_FIFO/BU2/XST_VCC
GND 		uut_tx/U_FIFO/BU2/XST_GND
VCC 		uut_tx/U_FIFO/BU2/XST_VCC

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+----------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type             | Direction | IO Standard | Drive    | Slew | Reg (s)      | Resistor | IOB      |
|                                    |                  |           |             | Strength | Rate |              |          | Delay    |
+----------------------------------------------------------------------------------------------------------------------------------------+
| BITSLIP_PAD                        | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |
| CLK200                             | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |
| CLK_USR                            | IOB              | INPUT     | LVCMOS25    |          |      |              |          |          |
| CLOCK_RX_N                         | IOB              | INPUT     | See master  |          |      |              |          |          |
| CLOCK_RX_P                         | IOB              | INPUT     | LVDS_25     |          |      |              |          | FIXED    |
| CLOCK_TX_N                         | IOBS             | OUTPUT    | See master  |          |      |              |          |          |
| CLOCK_TX_P                         | IOBM             | OUTPUT    | LVDSEXT_25  |          |      | ODDR         |          |          |
| DATA_RX_FIFO<0>                    | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF          |          |          |
| DATA_RX_FIFO<1>                    | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF          |          |          |
| DATA_RX_FIFO<2>                    | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF          |          |          |
| DATA_RX_FIFO<3>                    | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF          |          |          |
| DATA_RX_FIFO<4>                    | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF          |          |          |
| DATA_RX_FIFO<5>                    | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF          |          |          |
| DATA_RX_FIFO<6>                    | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF          |          |          |
| DATA_RX_FIFO<7>                    | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF          |          |          |
| DATA_RX_FIFO<8>                    | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF          |          |          |
| DATA_RX_FIFO<9>                    | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF          |          |          |
| DATA_RX_FIFO<10>                   | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF          |          |          |
| DATA_RX_FIFO<11>                   | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF          |          |          |
| DATA_RX_FIFO<12>                   | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF          |          |          |
| DATA_RX_FIFO<13>                   | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF          |          |          |
| DATA_RX_FIFO<14>                   | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF          |          |          |
| DATA_RX_FIFO<15>                   | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF          |          |          |
| DATA_RX_FIFO<16>                   | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF          |          |          |
| DATA_RX_FIFO<17>                   | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF          |          |          |
| DATA_RX_FIFO<18>                   | IOB              | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF          |          |          |