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📄 lvds_tx_rx_merge_map.mrp

📁 FPGA之间的LVDS传输
💻 MRP
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   not DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_DATA_10>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_DATA_03>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_DATA_11>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_DATA_04>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_DATA_12>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_DATA_05>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_DATA_13>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_DATA_06>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_DATA_14>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_DATA_07>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_DATA_15>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_DATA_08>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_DATA_09>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1362 - Unexpected programming for comp uut_tx/OSERDES_TX_Cntl with TRISTATE_WIDTH. DATA_RATE_TQ
   set DDR expects TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_MON_00>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_MON_01>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_MON_10>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_MON_02>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_MON_11>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_MON_03>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_MON_12>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_MON_04>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_MON_13>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_MON_05>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_MON_14>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_MON_06>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_MON_15>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_MON_07>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_MON_16>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_MON_08>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_MON_09>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/ISERDES_CLOCK_RX>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_MON_CNTL>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_CNTL>:<IODELAY_IODELAY>.  When DELAY_SRC is not
   DATAIN programming the DATAIN input pin is not used and will be ignored.WARNING:PhysDesignRules:1362 - Unexpected programming for comp uut_tx/OSERDES_TX_DATA_00 with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1362 - Unexpected programming for comp uut_tx/OSERDES_TX_DATA_01 with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1362 - Unexpected programming for comp uut_tx/OSERDES_TX_DATA_02 with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1362 - Unexpected programming for comp uut_tx/OSERDES_TX_DATA_10 with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1362 - Unexpected programming for comp uut_tx/OSERDES_TX_DATA_03 with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1362 - Unexpected programming for comp uut_tx/OSERDES_TX_DATA_11 with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1362 - Unexpected programming for comp uut_tx/OSERDES_TX_DATA_04 with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1362 - Unexpected programming for comp uut_tx/OSERDES_TX_DATA_12 with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1362 - Unexpected programming for comp uut_tx/OSERDES_TX_DATA_05 with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1362 - Unexpected programming for comp uut_tx/OSERDES_TX_DATA_13 with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1362 - Unexpected programming for comp uut_tx/OSERDES_TX_DATA_06 with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1362 - Unexpected programming for comp uut_tx/OSERDES_TX_DATA_14 with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1362 - Unexpected programming for comp uut_tx/OSERDES_TX_DATA_07 with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1362 - Unexpected programming for comp uut_tx/OSERDES_TX_DATA_15 with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1362 - Unexpected programming for comp uut_tx/OSERDES_TX_DATA_08 with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1362 - Unexpected programming for comp uut_tx/OSERDES_TX_DATA_09 with TRISTATE_WIDTH.
   DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_DATA_00>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_DATA_01>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_DATA_10>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_DATA_02>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_DATA_11>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_DATA_03>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_DATA_12>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_DATA_04>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_DATA_13>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_DATA_05>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_DATA_14>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_DATA_06>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_DATA_15>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_DATA_07>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_DATA_08>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_DATA_09>:<ISERDES_ISERDES>.  Useless CE2 input
   pin. With NUM_CE set 1 the CE2 input pin is being ignored.WARNING:PhysDesignRules:1325 - Dangling pins on block:<uut_rx/ISERDES_RX_CNTL>:<ISERDES_ISERDES>.  Useless CE2 input
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