lvds_tx_rx_merge_map.mrp

FPGA之间的LVDS传输

Release 10.1.02 Map K.37 (nt)
Xilinx Mapping Report File for Design 'lvds_tx_rx_merge'

Design Information
------------------
Command Line   : map -ise E:/ISEworks/LVDS/LVDS_4to1/xapp860.ise -intstyle ise -p xc5vsx50t-ff1136-1 -w -logic_opt off
-ol high -t 1 -cm area -pr o -k 6 -lc off -power off -o lvds_tx_rx_merge_map.ncd lvds_tx_rx_merge.ngd
lvds_tx_rx_merge.pcf 
Target Device  : xc5vsx50t
Target Package : ff1136
Target Speed   : -1
Mapper Version : virtex5 -- $Revision: 1.46.12.2 $
Mapped Date    : Mon Aug 25 17:16:54 2008

Design Summary
--------------
Number of errors:      0
Number of warnings:   89
Slice Logic Utilization:
  Number of Slice Registers:                   675 out of  32,640    2%
    Number used as Flip Flops:                 675
  Number of Slice LUTs:                        811 out of  32,640    2%
    Number used as logic:                      806 out of  32,640    2%
      Number using O6 output only:             806
    Number used as Memory:                       5 out of  12,480    1%
      Number used as Shift Register:             5
        Number using O6 output only:             5

Slice Logic Distribution:
  Number of occupied Slices:                   421 out of   8,160    5%
  Number of LUT Flip Flop pairs used:        1,048
    Number with an unused Flip Flop:           373 out of   1,048   35%
    Number with an unused LUT:                 237 out of   1,048   22%
    Number of fully used LUT-FF pairs:         438 out of   1,048   41%
    Number of unique control sets:              88
    Number of slice register sites lost
      to control set restrictions:             216 out of  32,640    1%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                       327 out of     480   68%
    IOB Flip Flops:                             67
    IOB Master Pads:                            18
    IOB Slave Pads:                             18

Specific Feature Utilization:
  Number of BlockRAM/FIFO:                       2 out of     132    1%
    Number using BlockRAM only:                  2
    Total primitives used:
      Number of 36k BlockRAM used:               2
    Total Memory used (KB):                     72 out of   4,752    1%
  Number of BUFG/BUFGCTRLs:                      4 out of      32   12%
    Number used as BUFGs:                        4
  Number of BUFIOs:                              1 out of      56    1%
  Number of BUFRs:                               1 out of      24    4%
  Number of ISERDESs:                           34
  Number of OSERDESs:                           17

Peak Memory Usage:  398 MB
Total REAL time to MAP completion:  1 mins 15 secs 
Total CPU time to MAP completion:   1 mins 9 secs 

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Control Set Information
Section 14 - Utilization by Hierarchy

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:LIT:243 - Logical network uut_tx/U_FIFO/full has no load.
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 4
   more times for the following (max. 5 shown):
   uut_tx/U_FIFO/empty,
   uut_rx/U_FIFO/full,
   uut_rx/U_FIFO/empty,
   uut_rx/U_FIFO/almost_full
   To see the details of these warning messages, please use the -detail switch.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_MON_00>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_MON_01>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_MON_02>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_MON_10>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_MON_03>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_MON_11>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_MON_04>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_MON_12>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_MON_05>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_MON_13>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_MON_06>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_MON_14>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_MON_07>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_MON_15>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_MON_08>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_MON_09>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_DATA_00>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_DATA_01>:<IODELAY_IODELAY>.  When DELAY_SRC is
   not DATAIN programming the DATAIN input pin is not used and will be ignored.
WARNING:PhysDesignRules:1412 - Dangling pins on block:<uut_rx/IODELAY_RX_DATA_02>:<IODELAY_IODELAY>.  When DELAY_SRC is