bit_align_machine.twr

FPGA之间的LVDS传输

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Release 10.1.02 Trace  (nt)
Copyright (c) 1995-2008 Xilinx, Inc.  All rights reserved.

K:\Xilinx\10.1\ISE\bin\nt\unwrapped\trce.exe -ise
E:/ISEworks/LVDS/xapp860/xapp860.ise -intstyle ise -v 3 -s 1 -xml
BIT_ALIGN_MACHINE BIT_ALIGN_MACHINE.ncd -o BIT_ALIGN_MACHINE.twr
BIT_ALIGN_MACHINE.pcf

Design file:              BIT_ALIGN_MACHINE.ncd
Physical constraint file: BIT_ALIGN_MACHINE.pcf
Device,package,speed:     xc5vsx50t,ff1136,-1 (PRODUCTION 1.61 2008-05-28, STEPPING level 0)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock RXCLKDIV
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  | Clock  |
Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
------------+------------+------------+------------------+--------+
RST         |    0.294(R)|    2.395(R)|RXCLKDIV_BUFGP    |   0.000|
RXDATA<0>   |    1.939(R)|    2.512(R)|RXCLKDIV_BUFGP    |   0.000|
RXDATA<1>   |    1.885(R)|    2.484(R)|RXCLKDIV_BUFGP    |   0.000|
RXDATA<2>   |    1.924(R)|    2.632(R)|RXCLKDIV_BUFGP    |   0.000|
RXDATA<3>   |    1.962(R)|    2.659(R)|RXCLKDIV_BUFGP    |   0.000|
RXDATA<4>   |    1.643(R)|    2.499(R)|RXCLKDIV_BUFGP    |   0.000|
RXDATA<5>   |    2.043(R)|    2.648(R)|RXCLKDIV_BUFGP    |   0.000|
SAP         |    1.725(R)|    2.356(R)|RXCLKDIV_BUFGP    |   0.000|
USE_BITSLIP |    1.547(R)|    2.246(R)|RXCLKDIV_BUFGP    |   0.000|
------------+------------+------------+------------------+--------+

Clock RXCLKDIV to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
BITSLIP     |    9.886(R)|RXCLKDIV_BUFGP    |   0.000|
DATA_ALIGNED|    8.464(R)|RXCLKDIV_BUFGP    |   0.000|
ICE         |    9.683(R)|RXCLKDIV_BUFGP    |   0.000|
INC         |    9.832(R)|RXCLKDIV_BUFGP    |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock RXCLKDIV
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
RXCLKDIV       |    3.886|         |         |         |
---------------+---------+---------+---------+---------+


Analysis completed Tue Aug 19 20:17:18 2008 
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Trace Settings:
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Trace Settings 

Peak Memory Usage: 250 MB