_primary.vhd

FPGA之间的LVDS传输

library verilog;
use verilog.vl_types.all;
entity synth_tb_lvds is
    port(
        usr_clk         : in     vl_logic;
        reset           : in     vl_logic;
        check_error     : out    vl_logic;
        usr_data_tx_vld : out    vl_logic;
        usr_data_tx_rdy : in     vl_logic;
        Data_bus_tx     : out    vl_logic_vector(0 to 63);
        usr_data_rx_vld : in     vl_logic;
        Data_bus_rx     : in     vl_logic_vector(0 to 63);
        TRAINING_DONE   : in     vl_logic;
        blind_timer_up  : out    vl_logic
    );
end synth_tb_lvds;