_primary.vhd

FPGA之间的LVDS传输

library verilog;
use verilog.vl_types.all;
entity bypass_bram is
    port(
        lnk_clk         : in     vl_logic;
        lnk_reset_n     : in     vl_logic;
        g_iram_addra    : in     vl_logic_vector(0 to 9);
        iram_doa        : out    vl_logic_vector(0 to 63);
        h_iram_addrb    : in     vl_logic_vector(0 to 9);
        iram_dob        : out    vl_logic_vector(0 to 63)
    );
end bypass_bram;