lvds_bist_top_tb.fdo

FPGA之间的LVDS传输

## NOTE:  Do not edit this file.
## Autogenerated by ProjNav (creatfdo.tcl) on Tue Nov 04 10:44:52 中国标准时间 2008
##
vlib work
vcom -explicit  -93 "seven_bit_reg_w_ce.vhd"
vcom -explicit  -93 "count_to_16x.vhd"
vcom -explicit  -93 "count_to_128.vhd"
vcom -explicit  -93 "RT_WINDOW_MONITOR.vhd"
vcom -explicit  -93 "RESOURCE_SHARING_CONTROL.vhd"
vcom -explicit  -93 "fifo_tx.vhd"
vcom -explicit  -93 "fifo_rx.vhd"
vcom -explicit  -93 "COUNT_TO_64.vhd"
vcom -explicit  -93 "BIT_ALIGN_MACHINE.vhd"
vcom -explicit  -93 "DDR_6TO1_16CHAN_RT_TX.vhd"
vcom -explicit  -93 "DDR_6TO1_16CHAN_RT_RX.vhd"
vlog +acc  "bypass_bram.v"
vlog +acc  "synth_tb_lvds.v"
vcom -explicit  -93 "lvds_tx_rx_merge.vhd"
vcom -explicit  -93 "lvds_dcm.vhd"
vcom -explicit  -93 "lvds_bist_top.vhd"
vcom -explicit  -93 "lvds_bist_top_tb.vhd"
vlog +acc  "E:/Xilinx10/ISE/verilog/src/glbl.v"
vsim -t 1ps   -L xilinxcorelib_ver -L unisims_ver -L unimacro_ver -L secureip -lib work lvds_bist_top_tb glbl
do {lvds_bist_top_tb_wave.fdo}
view wave
view structure
view signals
run 1000ns
do {lvds_bist_top_tb.udo}