bitgen.xmsgs

来自「FPGA之间的LVDS传输」· XMSGS 代码 · 共 172 行 · 第 1/2 页

XMSGS
172 行
字号
12
</msg>

<msg type="warning" file="PhysDesignRules" num="1412" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/IODELAY_RX_DATA_13</arg>&gt;:&lt;<arg fmt="%s" index="2">IODELAY_IODELAY</arg>&gt;.  When DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1412" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/IODELAY_RX_DATA_05</arg>&gt;:&lt;<arg fmt="%s" index="2">IODELAY_IODELAY</arg>&gt;.  When DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1412" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/IODELAY_RX_DATA_14</arg>&gt;:&lt;<arg fmt="%s" index="2">IODELAY_IODELAY</arg>&gt;.  When DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1412" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/IODELAY_RX_DATA_06</arg>&gt;:&lt;<arg fmt="%s" index="2">IODELAY_IODELAY</arg>&gt;.  When DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1412" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/IODELAY_RX_DATA_15</arg>&gt;:&lt;<arg fmt="%s" index="2">IODELAY_IODELAY</arg>&gt;.  When DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1412" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/IODELAY_RX_DATA_07</arg>&gt;:&lt;<arg fmt="%s" index="2">IODELAY_IODELAY</arg>&gt;.  When DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1412" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/IODELAY_RX_DATA_08</arg>&gt;:&lt;<arg fmt="%s" index="2">IODELAY_IODELAY</arg>&gt;.  When DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1412" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/IODELAY_RX_DATA_09</arg>&gt;:&lt;<arg fmt="%s" index="2">IODELAY_IODELAY</arg>&gt;.  When DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1412" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/IODELAY_RX_CNTL</arg>&gt;:&lt;<arg fmt="%s" index="2">IODELAY_IODELAY</arg>&gt;.  When DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1325" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/ISERDES_RX_DATA_00</arg>&gt;:&lt;<arg fmt="%s" index="2">ISERDES_ISERDES</arg>&gt;.  Useless CE2 input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1325" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/ISERDES_RX_DATA_01</arg>&gt;:&lt;<arg fmt="%s" index="2">ISERDES_ISERDES</arg>&gt;.  Useless CE2 input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1325" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/ISERDES_RX_DATA_10</arg>&gt;:&lt;<arg fmt="%s" index="2">ISERDES_ISERDES</arg>&gt;.  Useless CE2 input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1325" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/ISERDES_RX_DATA_02</arg>&gt;:&lt;<arg fmt="%s" index="2">ISERDES_ISERDES</arg>&gt;.  Useless CE2 input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1325" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/ISERDES_RX_DATA_11</arg>&gt;:&lt;<arg fmt="%s" index="2">ISERDES_ISERDES</arg>&gt;.  Useless CE2 input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1325" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/ISERDES_RX_DATA_03</arg>&gt;:&lt;<arg fmt="%s" index="2">ISERDES_ISERDES</arg>&gt;.  Useless CE2 input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1325" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/ISERDES_RX_DATA_12</arg>&gt;:&lt;<arg fmt="%s" index="2">ISERDES_ISERDES</arg>&gt;.  Useless CE2 input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1325" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/ISERDES_RX_DATA_04</arg>&gt;:&lt;<arg fmt="%s" index="2">ISERDES_ISERDES</arg>&gt;.  Useless CE2 input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1325" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/ISERDES_RX_DATA_13</arg>&gt;:&lt;<arg fmt="%s" index="2">ISERDES_ISERDES</arg>&gt;.  Useless CE2 input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1325" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/ISERDES_RX_DATA_05</arg>&gt;:&lt;<arg fmt="%s" index="2">ISERDES_ISERDES</arg>&gt;.  Useless CE2 input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1325" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/ISERDES_RX_DATA_14</arg>&gt;:&lt;<arg fmt="%s" index="2">ISERDES_ISERDES</arg>&gt;.  Useless CE2 input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1325" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/ISERDES_RX_DATA_06</arg>&gt;:&lt;<arg fmt="%s" index="2">ISERDES_ISERDES</arg>&gt;.  Useless CE2 input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1325" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/ISERDES_RX_DATA_15</arg>&gt;:&lt;<arg fmt="%s" index="2">ISERDES_ISERDES</arg>&gt;.  Useless CE2 input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1325" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/ISERDES_RX_DATA_07</arg>&gt;:&lt;<arg fmt="%s" index="2">ISERDES_ISERDES</arg>&gt;.  Useless CE2 input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1325" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/ISERDES_RX_DATA_08</arg>&gt;:&lt;<arg fmt="%s" index="2">ISERDES_ISERDES</arg>&gt;.  Useless CE2 input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1325" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/ISERDES_RX_DATA_09</arg>&gt;:&lt;<arg fmt="%s" index="2">ISERDES_ISERDES</arg>&gt;.  Useless CE2 input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1325" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/ISERDES_RX_CNTL</arg>&gt;:&lt;<arg fmt="%s" index="2">ISERDES_ISERDES</arg>&gt;.  Useless CE2 input pin. With NUM_CE set 1 the CE2 input pin is being ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1412" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/ISERDES_CLOCK_RX</arg>&gt;:&lt;<arg fmt="%s" index="2">IODELAY_IODELAY</arg>&gt;.  When DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
</msg>

</messages>
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bitgen.xmsgs - 源码说明

本页面展示了「FPGA之间的LVDS传输」中的 bitgen.xmsgs 源码文件，采用 XMSGS 编程语言编写，共 172 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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