bitgen.xmsgs

FPGA之间的LVDS传输

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<messages>
<msg type="info" file="Bitgen" num="40" delta="unknown" >Replacing &quot;<arg fmt="%s" index="1">Auto</arg>&quot; with &quot;<arg fmt="%s" index="2">NoWait</arg>&quot; for option &quot;<arg fmt="%s" index="3">Match_cycle</arg>&quot;.  Most commonly, bitgen has determined and will use a specific value instead of the generic command-line value of &quot;Auto&quot;.  Alternately, this message appears if the same option is specified multiple times on the command-line.  In this case, the option listed last will be used.
</msg>

<msg type="info" file="PhysDesignRules" num="1437" delta="unknown" >To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM_ADV comp <arg fmt="%s" index="1">u_DCM/DCM_ADV_INST</arg>, consult the device Data Sheet.
</msg>

<msg type="warning" file="PhysDesignRules" num="1362" delta="unknown" >Unexpected programming for comp <arg fmt="%s" index="1">u_lvds/uut_tx/OSERDES_TX_Cntl</arg> with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
</msg>

<msg type="warning" file="PhysDesignRules" num="1362" delta="unknown" >Unexpected programming for comp <arg fmt="%s" index="1">u_lvds/uut_tx/OSERDES_TX_DATA_00</arg> with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
</msg>

<msg type="warning" file="PhysDesignRules" num="1362" delta="unknown" >Unexpected programming for comp <arg fmt="%s" index="1">u_lvds/uut_tx/OSERDES_TX_DATA_01</arg> with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
</msg>

<msg type="warning" file="PhysDesignRules" num="1362" delta="unknown" >Unexpected programming for comp <arg fmt="%s" index="1">u_lvds/uut_tx/OSERDES_TX_DATA_10</arg> with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
</msg>

<msg type="warning" file="PhysDesignRules" num="1362" delta="unknown" >Unexpected programming for comp <arg fmt="%s" index="1">u_lvds/uut_tx/OSERDES_TX_DATA_02</arg> with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
</msg>

<msg type="warning" file="PhysDesignRules" num="1362" delta="unknown" >Unexpected programming for comp <arg fmt="%s" index="1">u_lvds/uut_tx/OSERDES_TX_DATA_11</arg> with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
</msg>

<msg type="warning" file="PhysDesignRules" num="1362" delta="unknown" >Unexpected programming for comp <arg fmt="%s" index="1">u_lvds/uut_tx/OSERDES_TX_DATA_03</arg> with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
</msg>

<msg type="warning" file="PhysDesignRules" num="1362" delta="unknown" >Unexpected programming for comp <arg fmt="%s" index="1">u_lvds/uut_tx/OSERDES_TX_DATA_12</arg> with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
</msg>

<msg type="warning" file="PhysDesignRules" num="1362" delta="unknown" >Unexpected programming for comp <arg fmt="%s" index="1">u_lvds/uut_tx/OSERDES_TX_DATA_04</arg> with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
</msg>

<msg type="warning" file="PhysDesignRules" num="1362" delta="unknown" >Unexpected programming for comp <arg fmt="%s" index="1">u_lvds/uut_tx/OSERDES_TX_DATA_13</arg> with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
</msg>

<msg type="warning" file="PhysDesignRules" num="1362" delta="unknown" >Unexpected programming for comp <arg fmt="%s" index="1">u_lvds/uut_tx/OSERDES_TX_DATA_05</arg> with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
</msg>

<msg type="warning" file="PhysDesignRules" num="1362" delta="unknown" >Unexpected programming for comp <arg fmt="%s" index="1">u_lvds/uut_tx/OSERDES_TX_DATA_14</arg> with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
</msg>

<msg type="warning" file="PhysDesignRules" num="1362" delta="unknown" >Unexpected programming for comp <arg fmt="%s" index="1">u_lvds/uut_tx/OSERDES_TX_DATA_06</arg> with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
</msg>

<msg type="warning" file="PhysDesignRules" num="1362" delta="unknown" >Unexpected programming for comp <arg fmt="%s" index="1">u_lvds/uut_tx/OSERDES_TX_DATA_15</arg> with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
</msg>

<msg type="warning" file="PhysDesignRules" num="1362" delta="unknown" >Unexpected programming for comp <arg fmt="%s" index="1">u_lvds/uut_tx/OSERDES_TX_DATA_07</arg> with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
</msg>

<msg type="warning" file="PhysDesignRules" num="1362" delta="unknown" >Unexpected programming for comp <arg fmt="%s" index="1">u_lvds/uut_tx/OSERDES_TX_DATA_08</arg> with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
</msg>

<msg type="warning" file="PhysDesignRules" num="1362" delta="unknown" >Unexpected programming for comp <arg fmt="%s" index="1">u_lvds/uut_tx/OSERDES_TX_DATA_09</arg> with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
</msg>

<msg type="warning" file="PhysDesignRules" num="1412" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/IODELAY_RX_DATA_00</arg>&gt;:&lt;<arg fmt="%s" index="2">IODELAY_IODELAY</arg>&gt;.  When DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1412" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/IODELAY_RX_DATA_01</arg>&gt;:&lt;<arg fmt="%s" index="2">IODELAY_IODELAY</arg>&gt;.  When DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1412" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/IODELAY_RX_DATA_10</arg>&gt;:&lt;<arg fmt="%s" index="2">IODELAY_IODELAY</arg>&gt;.  When DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1412" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/IODELAY_RX_DATA_02</arg>&gt;:&lt;<arg fmt="%s" index="2">IODELAY_IODELAY</arg>&gt;.  When DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1412" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/IODELAY_RX_DATA_11</arg>&gt;:&lt;<arg fmt="%s" index="2">IODELAY_IODELAY</arg>&gt;.  When DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1412" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/IODELAY_RX_DATA_03</arg>&gt;:&lt;<arg fmt="%s" index="2">IODELAY_IODELAY</arg>&gt;.  When DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1412" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/IODELAY_RX_DATA_12</arg>&gt;:&lt;<arg fmt="%s" index="2">IODELAY_IODELAY</arg>&gt;.  When DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.
</msg>

<msg type="warning" file="PhysDesignRules" num="1412" delta="unknown" >Dangling pins on block:&lt;<arg fmt="%s" index="1">u_lvds/uut_rx/IODELAY_RX_DATA_04</arg>&gt;:&lt;<arg fmt="%s" index="2">IODELAY_IODELAY</arg>&gt;.  When DELAY_SRC is not DATAIN programming the DATAIN input pin is not used and will be ignored.