map.xmsgs

FPGA之间的LVDS传输

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<messages>
<msg type="warning" file="Map" num="236" delta="unknown" >The MAP option, &quot;-k&quot; (MAP to Input Functions), will be  disabled for this architecture in the next software release.

</msg>

<msg type="warning" file="LIT" num="243" delta="unknown" >Logical network <arg fmt="%s" index="1">u_DCM/CLK0_OUT</arg> has no load.
</msg>

<msg type="warning" file="LIT" num="395" delta="unknown" >The above <arg fmt="%s" index="1">warning</arg> message <arg fmt="%s" index="2">base_net_load_rule</arg> is repeated <arg fmt="%d" index="3">8</arg> more times for the following (max. 5 shown):
<arg fmt="%s" index="4">u_lvds/uut_tx/U_FIFO/full,
u_lvds/uut_tx/U_FIFO/empty,
u_lvds/uut_tx/U_FIFO/BU2/U0/grf.rf/gcx.clkx/wr_pntr_gc_asreg&lt;0&gt;,
u_lvds/uut_rx/RT_WINDOW_MONITOR_0/DATA_ALIGNED_RT,
u_lvds/uut_rx/U_FIFO/full</arg>
To see the details of these <arg fmt="%s" index="5">warning</arg> messages, please use the -detail switch.
</msg>

<msg type="info" file="MapLib" num="562" delta="unknown" >No environment variables are currently set.
</msg>

<msg type="info" file="LIT" num="244" delta="unknown" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
</msg>

<msg type="warning" file="Pack" num="1186" delta="unknown" >One or more I/O components have conflicting property values.  For each occurrence, the system will use the property value attached to the pad.  Otherwise, the system will use the first property value read.  To view each occurrence, create a detailed map report (run map using the -detail option).
</msg>

<msg type="warning" file="Pack" num="2574" delta="unknown" >The F7 multiplexer symbol &quot;<arg fmt="%s" index="1">U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/YES_LUT6.U_CS_MUX/I6.U_MUX64/YES_LUT6.U_MUX16A/U_MUX8B/YES_LUT6.U_MUXF7</arg>&quot; and its I1 input driver &quot;<arg fmt="%s" index="2">U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/iSTAT&lt;11&gt;658</arg>&quot; were implemented suboptimally in the same slice component. The function generator could not be placed directly driving the F7 multiplexer. The design will exhibit suboptimal timing.
</msg>

<msg type="warning" file="Pack" num="2574" delta="unknown" >The F7 multiplexer symbol &quot;<arg fmt="%s" index="1">U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/YES_LUT6.U_CS_MUX/I6.U_MUX64/YES_LUT6.U_MUX16B/U_MUX8B/YES_LUT6.U_MUXF7</arg>&quot; and its I1 input driver &quot;<arg fmt="%s" index="2">U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/iSTAT&lt;11&gt;658</arg>&quot; were implemented suboptimally in the same slice component. The function generator could not be placed directly driving the F7 multiplexer. The design will exhibit suboptimal timing.
</msg>

<msg type="warning" file="Pack" num="2143" delta="unknown" >The function generator &quot;<arg fmt="%s" index="1">U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/iSTAT&lt;11&gt;658</arg>&quot; failed to merge with F7 multiplexer &quot;<arg fmt="%s" index="2">U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/YES_LUT6.U_CS_MUX/I6.U_MUX64/YES_LUT6.U_MUX16B/U_MUX8A/YES_LUT6.U_MUXF7</arg>&quot;.  <arg fmt="%z" index="3">There are more than two MUXF7 wide function muxes.</arg>  The design will exhibit suboptimal timing.
</msg>

<msg type="warning" file="Pack" num="2143" delta="unknown" >The function generator &quot;<arg fmt="%s" index="1">U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/iSTAT&lt;11&gt;658</arg>&quot; failed to merge with F7 multiplexer &quot;<arg fmt="%s" index="2">U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/YES_LUT6.U_CS_MUX/I6.U_MUX64/YES_LUT6.U_MUX16C/U_MUX8B/YES_LUT6.U_MUXF7</arg>&quot;.  <arg fmt="%z" index="3">There are more than two MUXF7 wide function muxes.</arg>  The design will exhibit suboptimal timing.
</msg>

<msg type="warning" file="Pack" num="2143" delta="unknown" >The function generator &quot;<arg fmt="%s" index="1">U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/iSTAT&lt;11&gt;658</arg>&quot; failed to merge with F7 multiplexer &quot;<arg fmt="%s" index="2">U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/YES_LUT6.U_CS_MUX/I6.U_MUX64/YES_LUT6.U_MUX16C/U_MUX8A/YES_LUT6.U_MUXF7</arg>&quot;.  <arg fmt="%z" index="3">There are more than two MUXF7 wide function muxes.</arg>  The design will exhibit suboptimal timing.
</msg>

<msg type="warning" file="Pack" num="2143" delta="unknown" >The function generator &quot;<arg fmt="%s" index="1">U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/iSTAT&lt;11&gt;658</arg>&quot; failed to merge with F7 multiplexer &quot;<arg fmt="%s" index="2">U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/YES_LUT6.U_CS_MUX/I6.U_MUX64/YES_LUT6.U_MUX16D/U_MUX8B/YES_LUT6.U_MUXF7</arg>&quot;.  <arg fmt="%z" index="3">There are more than two MUXF7 wide function muxes.</arg>  The design will exhibit suboptimal timing.
</msg>

<msg type="warning" file="Pack" num="2143" delta="unknown" >The function generator &quot;<arg fmt="%s" index="1">U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/iSTAT&lt;11&gt;658</arg>&quot; failed to merge with F7 multiplexer &quot;<arg fmt="%s" index="2">U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/YES_LUT6.U_CS_MUX/I6.U_MUX64/YES_LUT6.U_MUX16D/U_MUX8A/YES_LUT6.U_MUXF7</arg>&quot;.  <arg fmt="%z" index="3">There are more than two MUXF7 wide function muxes.</arg>  The design will exhibit suboptimal timing.
</msg>

<msg type="warning" file="Pack" num="2145" delta="unknown" >The F7 mux &quot;<arg fmt="%s" index="1">U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/YES_LUT6.U_CS_MUX/I6.U_MUX64/YES_LUT6.U_MUX16B/U_MUX8B/YES_LUT6.U_MUXF7</arg>&quot; failed to merge with F8 mux &quot;<arg fmt="%s" index="2">U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/YES_LUT6.U_CS_MUX/I6.U_MUX64/YES_LUT6.U_MUX16B/YES_LUT6.U_MUXF8</arg>&quot;.  <arg fmt="%z" index="3">There are more than two MUXF7 wide function muxes.</arg>  The design will exhibit suboptimal timing.
</msg>

<msg type="warning" file="Pack" num="2145" delta="unknown" >The F7 mux &quot;<arg fmt="%s" index="1">U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/YES_LUT6.U_CS_MUX/I6.U_MUX64/YES_LUT6.U_MUX16A/U_MUX8B/YES_LUT6.U_MUXF7</arg>&quot; failed to merge with F8 mux &quot;<arg fmt="%s" index="2">U_ila_pro_0/U0/I_YES_D.U_ILA/U_STAT/U_SMUX/YES_LUT6.U_CS_MUX/I6.U_MUX64/YES_LUT6.U_MUX16A/YES_LUT6.U_MUXF8</arg>&quot;.  <arg fmt="%z" index="3">There are more than two MUXF7 wide function muxes.</arg>  The design will exhibit suboptimal timing.
</msg>

<msg type="info" file="Pack" num="1716" delta="unknown" >Initializing temperature to <arg fmt="%0.3f" index="1">85.000</arg> Celsius. (default - Range: <arg fmt="%0.3f" index="2">0.000</arg> to <arg fmt="%0.3f" index="3">85.000</arg> Celsius)
</msg>

<msg type="info" file="Pack" num="1720" delta="unknown" >Initializing voltage to <arg fmt="%0.3f" index="1">0.950</arg> Volts. (default - Range: <arg fmt="%0.3f" index="2">0.950</arg> to <arg fmt="%0.3f" index="3">1.050</arg> Volts)
</msg>

<msg type="info" file="Map" num="215" delta="unknown" >The Interim Design Summary has been generated in the MAP Report (.mrp).
</msg>

<msg type="info" file="Place" num="834" delta="unknown" >Only a subset of IOs are locked. Out of <arg fmt="%d" index="1">182</arg> IOs, <arg fmt="%d" index="2">76</arg> are locked and <arg fmt="%d" index="3">106</arg> are not locked. <arg fmt="%s" index="4">If you would like to print the names of these IOs, please set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1.</arg> 
</msg>

<msg type="info" file="Pack" num="1650" delta="unknown" >Map created a placed design.
</msg>

<msg type="info" file="PhysDesignRules" num="1437" delta="unknown" >To achieve optimal frequency synthesis performance with the CLKFX and CLKFX180 outputs of the DCM_ADV comp <arg fmt="%s" index="1">u_DCM/DCM_ADV_INST</arg>, consult the device Data Sheet.
</msg>

<msg type="warning" file="PhysDesignRules" num="1362" delta="unknown" >Unexpected programming for comp <arg fmt="%s" index="1">u_lvds/uut_tx/OSERDES_TX_Cntl</arg> with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
</msg>

<msg type="warning" file="PhysDesignRules" num="1362" delta="unknown" >Unexpected programming for comp <arg fmt="%s" index="1">u_lvds/uut_tx/OSERDES_TX_DATA_00</arg> with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
</msg>

<msg type="warning" file="PhysDesignRules" num="1362" delta="unknown" >Unexpected programming for comp <arg fmt="%s" index="1">u_lvds/uut_tx/OSERDES_TX_DATA_01</arg> with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
</msg>

<msg type="warning" file="PhysDesignRules" num="1362" delta="unknown" >Unexpected programming for comp <arg fmt="%s" index="1">u_lvds/uut_tx/OSERDES_TX_DATA_10</arg> with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
</msg>

<msg type="warning" file="PhysDesignRules" num="1362" delta="unknown" >Unexpected programming for comp <arg fmt="%s" index="1">u_lvds/uut_tx/OSERDES_TX_DATA_02</arg> with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
</msg>

<msg type="warning" file="PhysDesignRules" num="1362" delta="unknown" >Unexpected programming for comp <arg fmt="%s" index="1">u_lvds/uut_tx/OSERDES_TX_DATA_11</arg> with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
</msg>

<msg type="warning" file="PhysDesignRules" num="1362" delta="unknown" >Unexpected programming for comp <arg fmt="%s" index="1">u_lvds/uut_tx/OSERDES_TX_DATA_03</arg> with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
</msg>

<msg type="warning" file="PhysDesignRules" num="1362" delta="unknown" >Unexpected programming for comp <arg fmt="%s" index="1">u_lvds/uut_tx/OSERDES_TX_DATA_12</arg> with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
</msg>

<msg type="warning" file="PhysDesignRules" num="1362" delta="unknown" >Unexpected programming for comp <arg fmt="%s" index="1">u_lvds/uut_tx/OSERDES_TX_DATA_04</arg> with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
</msg>

<msg type="warning" file="PhysDesignRules" num="1362" delta="unknown" >Unexpected programming for comp <arg fmt="%s" index="1">u_lvds/uut_tx/OSERDES_TX_DATA_13</arg> with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
</msg>

<msg type="warning" file="PhysDesignRules" num="1362" delta="unknown" >Unexpected programming for comp <arg fmt="%s" index="1">u_lvds/uut_tx/OSERDES_TX_DATA_05</arg> with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
</msg>

<msg type="warning" file="PhysDesignRules" num="1362" delta="unknown" >Unexpected programming for comp <arg fmt="%s" index="1">u_lvds/uut_tx/OSERDES_TX_DATA_14</arg> with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
</msg>

<msg type="warning" file="PhysDesignRules" num="1362" delta="unknown" >Unexpected programming for comp <arg fmt="%s" index="1">u_lvds/uut_tx/OSERDES_TX_DATA_06</arg> with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
</msg>

<msg type="warning" file="PhysDesignRules" num="1362" delta="unknown" >Unexpected programming for comp <arg fmt="%s" index="1">u_lvds/uut_tx/OSERDES_TX_DATA_15</arg> with TRISTATE_WIDTH. DATA_RATE_TQ set DDR expects TRISTATE_WIDTH to be set 4. 
</msg>