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ARM Macro Assembler Page 1
1 00000000 ;/******************************************************
*****************/
2 00000000 ;/* This file is part of the CA ARM C Compiler package
*/
3 00000000 ;/* Copyright KEIL ELEKTRONIK GmbH 2002-2004
*/
4 00000000 ;/******************************************************
*****************/
5 00000000 ;/*
*/
6 00000000 ;/* SAM7S.S: Startup file for Atmel AT91SAM7S device s
eries */
7 00000000 ;/*
*/
8 00000000 ;/******************************************************
*****************/
9 00000000
10 00000000
11 00000000 ;//*** <<< Use Configuration Wizard in Context Menu >>>
***
12 00000000
13 00000000
14 00000000 ; *** Startup Code (executed after Reset) ***
15 00000000
16 00000000
17 00000000 ; Standard definitions of Mode bits and Interrupt (I & F
) flags in PSRs
18 00000000
19 00000000 00000010
Mode_USR
EQU 0x10
20 00000000 00000011
Mode_FIQ
EQU 0x11
21 00000000 00000012
Mode_IRQ
EQU 0x12
22 00000000 00000013
Mode_SVC
EQU 0x13
23 00000000 00000017
Mode_ABT
EQU 0x17
24 00000000 0000001B
Mode_UND
EQU 0x1B
25 00000000 0000001F
Mode_SYS
EQU 0x1F
26 00000000
27 00000000 00000080
I_Bit EQU 0x80 ; when I bit is set, IRQ is
disabled
28 00000000 00000040
F_Bit EQU 0x40 ; when F bit is set, FIQ is
disabled
29 00000000
30 00000000
31 00000000 ; Internal Memory Base Addresses
ARM Macro Assembler Page 2
32 00000000 00100000
FLASH_BASE
EQU 0x00100000
33 00000000 00200000
RAM_BASE
EQU 0x00200000
34 00000000
35 00000000
36 00000000 ;// <h> Stack Configuration
37 00000000 ;// <o> Top of Stack Address <0x0-0xFFFFFFFF:4>
38 00000000 ;// <h> Stack Sizes (in Bytes)
39 00000000 ;// <o1> Undefined Mode <0x0-0xFFFFFFFF:4>
40 00000000 ;// <o2> Supervisor Mode <0x0-0xFFFFFFFF:4>
41 00000000 ;// <o3> Abort Mode <0x0-0xFFFFFFFF:4>
42 00000000 ;// <o4> Fast Interrupt Mode <0x0-0xFFFFFFFF:4>
43 00000000 ;// <o5> Interrupt Mode <0x0-0xFFFFFFFF:4>
44 00000000 ;// <o6> User/System Mode <0x0-0xFFFFFFFF:4>
45 00000000 ;// </h>
46 00000000 ;// </h>
47 00000000
48 00000000 00204000
Top_Stack
EQU 0x00204000
49 00000000 00000004
UND_Stack_Size
EQU 0x00000004
50 00000000 00000004
SVC_Stack_Size
EQU 0x00000004
51 00000000 00000004
ABT_Stack_Size
EQU 0x00000004
52 00000000 00000004
FIQ_Stack_Size
EQU 0x00000004
53 00000000 00000080
IRQ_Stack_Size
EQU 0x00000080
54 00000000 00000400
USR_Stack_Size
EQU 0x00000400
55 00000000
56 00000000
57 00000000 ; Embedded Flash Controller (EFC) definitions
58 00000000 FFFFFF00
EFC_BASE
EQU 0xFFFFFF00 ; EFC Base Address
59 00000000 00000060
EFC_FMR EQU 0x60 ; EFC_FMR Offset
60 00000000
61 00000000 ;// <e> Embedded Flash Controller (EFC)
62 00000000 ;// <o1.16..23> FMCN: Flash Microsecond Cycle Number <
0-255>
63 00000000 ;// <i> Number of Master Clock Cycles in 1
us
64 00000000 ;// <o1.8..9> FWS: Flash Wait State
65 00000000 ;// <0=> Read: 1 cycle / Write: 2 cycles
66 00000000 ;// <1=> Read: 2 cycle / Write: 3 cycles
67 00000000 ;// <2=> Read: 3 cycle / Write: 4 cycles
ARM Macro Assembler Page 3
68 00000000 ;// <3=> Read: 4 cycle / Write: 4 cycles
69 00000000 ;// </e>
70 00000000 00000001
EFC_SETUP
EQU 1
71 00000000 00320100
EFC_FMR_Val
EQU 0x00320100
72 00000000
73 00000000
74 00000000 ; Watchdog Timer (WDT) definitions
75 00000000 FFFFFD40
WDT_BASE
EQU 0xFFFFFD40 ; WDT Base Address
76 00000000 00000004
WDT_MR EQU 0x04 ; WDT_MR Offset
77 00000000
78 00000000 ;// <e> Watchdog Timer (WDT)
79 00000000 ;// <o1.0..11> WDV: Watchdog Counter Value <0-4095>
80 00000000 ;// <o1.16..27> WDD: Watchdog Delta Value <0-4095>
81 00000000 ;// <o1.12> WDFIEN: Watchdog Fault Interrupt Enabl
e
82 00000000 ;// <o1.13> WDRSTEN: Watchdog Reset Enable
83 00000000 ;// <o1.14> WDRPROC: Watchdog Reset Processor
84 00000000 ;// <o1.28> WDDBGHLT: Watchdog Debug Halt
85 00000000 ;// <o1.29> WDIDLEHLT: Watchdog Idle Halt
86 00000000 ;// <o1.15> WDDIS: Watchdog Disable
87 00000000 ;// </e>
88 00000000 00000001
WDT_SETUP
EQU 1
89 00000000 00008000
WDT_MR_Val
EQU 0x00008000
90 00000000
91 00000000
92 00000000 ; Power Mangement Controller (PMC) definitions
93 00000000 FFFFFC00
PMC_BASE
EQU 0xFFFFFC00 ; PMC Base Address
94 00000000 00000020
PMC_MOR EQU 0x20 ; PMC_MOR Offset
95 00000000 00000024
PMC_MCFR
EQU 0x24 ; PMC_MCFR Offset
96 00000000 0000002C
PMC_PLLR
EQU 0x2C ; PMC_PLLR Offset
97 00000000 00000030
PMC_MCKR
EQU 0x30 ; PMC_MCKR Offset
98 00000000 00000068
PMC_SR EQU 0x68 ; PMC_SR Offset
99 00000000 00000001
PMC_MOSCEN
EQU (1<<0) ; Main Oscillator Enable
100 00000000 00000002
PMC_OSCBYPASS
EQU (1<<1) ; Main Oscillator Bypass
ARM Macro Assembler Page 4
101 00000000 0000FF00
PMC_OSCOUNT
EQU (0xFF<<8) ; Main OScillator Start-up T
ime
102 00000000 000000FF
PMC_DIV EQU (0xFF<<0) ; PLL Divider
103 00000000 00003F00
PMC_PLLCOUNT
EQU (0x3F<<8) ; PLL Lock Counter
104 00000000 0000C000
PMC_OUT EQU (0x03<<14) ; PLL Clock Frequency Range
105 00000000 07FF0000
PMC_MUL EQU (0x7FF<<16) ; PLL Multiplier
106 00000000 30000000
PMC_USBDIV
EQU (0x03<<28) ; USB Clock Divider
107 00000000 00000003
PMC_CSS EQU (3<<0) ; Clock Source Selection
108 00000000 0000001C
PMC_PRES
EQU (7<<2) ; Prescaler Selection
109 00000000 00000001
PMC_MOSCS
EQU (1<<0) ; Main Oscillator Stable
110 00000000 00000004
PMC_LOCK
EQU (1<<2) ; PLL Lock Status
111 00000000
112 00000000 ;// <e> Power Mangement Controller (PMC)
113 00000000 ;// <h> Main Oscillator
114 00000000 ;// <o1.0> MOSCEN: Main Oscillator Enable
115 00000000 ;// <o1.1> OSCBYPASS: Oscillator Bypass
116 00000000 ;// <o1.8..15> OSCCOUNT: Main Oscillator Startup Ti
me <0-255>
117 00000000 ;// </h>
118 00000000 ;// <h> Phase Locked Loop (PLL)
119 00000000 ;// <o2.0..7> DIV: PLL Divider <0-255>
120 00000000 ;// <o2.16..26> MUL: PLL Multiplier <0-2047>
121 00000000 ;// <i> PLL Output is multiplied by MUL+
1
122 00000000 ;// <o2.14..15> OUT: PLL Clock Frequency Range
123 00000000 ;// <0=> 80..160MHz <1=> Reserved
124 00000000 ;// <2=> 150..220MHz <3=> Reserved
125 00000000 ;// <o2.8..13> PLLCOUNT: PLL Lock Counter <0-63>
126 00000000 ;// <o2.28..29> USBDIV: USB Clock Divider
127 00000000 ;// <0=> None <1=> 2 <2=> 4 <3=> Rese
rved
128 00000000 ;// </h>
129 00000000 ;// <o3.0..1> CSS: Clock Source Selection
130 00000000 ;// <0=> Slow Clock
131 00000000 ;// <1=> Main Clock
132 00000000 ;// <2=> Reserved
133 00000000 ;// <3=> PLL Clock
134 00000000 ;// <o3.2..4> PRES: Prescaler
135 00000000 ;// <0=> None
136 00000000 ;// <1=> Clock / 2 <2=> Clock / 4
137 00000000 ;// <3=> Clock / 8 <4=> Clock / 16
138 00000000 ;// <5=> Clock / 32 <6=> Clock / 64
139 00000000 ;// <7=> Reserved
ARM Macro Assembler Page 5
140 00000000 ;// </e>
141 00000000 00000001
PMC_SETUP
EQU 1
142 00000000 00000601
PMC_MOR_Val
EQU 0x00000601
143 00000000 00191C05
PMC_PLLR_Val
EQU 0x00191C05
144 00000000 00000007
PMC_MCKR_Val
EQU 0x00000007
145 00000000
146 00000000
147 00000000
148 00000000 PRESERVE8
149 00000000 AREA START, CODE, READONLY
150 00000000 CODE32
151 00000000
152 00000000 ENTRY
153 00000000 EXPORT RESET
154 00000000 RESET
155 00000000 E59FF018 LDR PC,Reset_Addr
156 00000004 E59FF018 LDR PC,Undef_Addr
157 00000008 E59FF018 LDR PC,SWI_Addr
158 0000000C E59FF018 LDR PC,PAbt_Addr
159 00000010 E59FF018 LDR PC,DAbt_Addr
160 00000014 E1A00000 NOP ; Reserved Vector
161 00000018 ; LDR PC,IRQ_Addr
162 00000018 E51FFF20 LDR PC,[PC,#-0xF20] ; Vector From AIC_IVR
163 0000001C ; LDR PC,FIQ_Addr
164 0000001C E51FFF20 LDR PC,[PC,#-0xF20] ; Vector From AIC_FVR
165 00000020
166 00000020 00000000
Reset_Addr
DCD Reset_Handler
167 00000024 00000000
Undef_Addr
DCD Undef_Handler
168 00000028 00000000
SWI_Addr
DCD SWI_Handler
169 0000002C 00000000
PAbt_Addr
DCD PAbt_Handler
170 00000030 00000000
DAbt_Addr
DCD DAbt_Handler
171 00000034 00000000 DCD 0 ; Reserved Address
172 00000038 00000000
IRQ_Addr
DCD IRQ_Handler
173 0000003C 00000000
FIQ_Addr
DCD FIQ_Handler
174 00000040
175 00000040 EAFFFFFE
Undef_Handler
ARM Macro Assembler Page 6
B Undef_Handler
176 00000044 EAFFFFFE
SWI_Handler
B SWI_Handler
177 00000048 EAFFFFFE
PAbt_Handler
B PAbt_Handler
178 0000004C EAFFFFFE
DAbt_Handler
B DAbt_Handler
179 00000050 EAFFFFFE
IRQ_Handler
B IRQ_Handler
180 00000054 EAFFFFFE
FIQ_Handler
B FIQ_Handler
181 00000058
182 00000058
183 00000058 ; Reset Handler
184 00000058
185 00000058 Reset_Handler
186 00000058
187 00000058
188 00000058 ; Setup EFC
189 00000058 IF EFC_SETUP <> 0
190 00000058 E3E000FF LDR R0, =EFC_BASE
191 0000005C E59F1090 LDR R1, =EFC_FMR_Val
192 00000060 E5801060 STR R1, [R0, #EFC_FMR]
193 00000064 ENDIF
194 00000064
195 00000064
196 00000064 ; Setup WDT
197 00000064 IF WDT_SETUP <> 0
198 00000064 E59F008C LDR R0, =WDT_BASE
199 00000068 E3A01C80 LDR R1, =WDT_MR_Val
200 0000006C E5801004 STR R1, [R0, #WDT_MR]
201 00000070 ENDIF
202 00000070
203 00000070
204 00000070 ; Setup PMC
205 00000070 IF PMC_SETUP <> 0
206 00000070 E59F0084 LDR R0, =PMC_BASE
207 00000074
208 00000074 ; Setup Main Oscillator
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