6.c

ATMEL用IO模拟直接驱动内部无控制器的夏普320240

		//AIC_IECR = 0x7ff4;		//中断使能命令寄存器只写–- 0 = 无效。1 = 使能相应中断。
		AIC_IDCR = 0xffffffff;// 中断禁用命令寄存器只写–- 0 = 无效。1 = 禁用相应中断。
		AIC_ICCR = 0xffffffff;// 中断清除命令寄存器只写–- 0 = 无效。1 = 清除相应中断。
		//AIC_ISCR = 0xffffffff;//中断置位命令寄存器只写–- 0 = 无效。1 = 置位相应中断
		//AIC_EOICR 中断结束命令寄存器只写–-中断处理程序用中断结束命令寄存器指示中断处理结束。因为只需要向该寄存器地址写值以标识中断处理结束，所以可向其写入任意值。
		//AIC_SPU 伪中断向量寄存器读/ 写0x0--用户可在该寄存器中存储伪中断处理程序的地址。当出现未中断时，写入该寄存器的值为AIC_IVR 的返回值，类似的发生伪快速中断时，写入该寄存器的值为AIC_IVR 的返回值。
		//AIC_DCR 调试控制寄存器读/ 写0x0-- 0-0 0 = 保护模式禁用。1 = 保护模式使能。1-1 0 = nIRQ 与nFIQ 线由AIC 控制。1 = nIRQ 与nFIQ 线置于无效状态。
		//AIC_FFER = 0xffffffff;		//快速强制使能寄存器只写–- 0 = 无效。1 = 使能相应中断快速强制特性
		AIC_FFDR = 0xffffffff;// 快速强制禁用寄存器只写–- 0 = 无效。1 = 禁用相应中断快速强制特性
		//AIC_FFSR 快速强制状态寄存器只读0x0--0 = 禁用相应中断的快速强制特性。1 = 使能相应中断的快速强制特性。
}
//上电延时
void hssdys(void)
{
	PMC_SCER = 0xffffffff;		//系统时钟使能寄存器
	PMC_PCER = 0XFFFFFFFF;		//外设时钟使能寄存器
	if((PIO_PDSR&set_16)==0)
	{
		while(1)
		{
			hsqkmg();
			PMC_SCER = 0xffffffff;		//系统时钟使能寄存器
			PMC_PCER = 0XFFFFFFFF;		//外设时钟使能寄存器
			CKGR_MOR = 0x0000ff01;		//时钟发生器主振荡器寄存器
			PMC_MCKR = 0x00000001;		//PMC 主机时钟寄存器
		}
	}
}
//时钟设置
void hsszsz(void)
{
	PMC_SCER = 0xffffffff;		//系统时钟使能寄存器
	PMC_PCER = 0XFFFFFFFF;		//外设时钟使能寄存器
	CKGR_MOR = 0x0000ff01;		//时钟发生器主振荡器寄存器
	PMC_MCKR = 0x00000001;		//PMC 主机时钟寄存器
	//CKGR_PLLR = 0x00040805;
} 		
//清看门狗
void hsqkmg(void)
{
	WDT_MR = 0x30000000;
	WDT_CR = 0xa5000001;		//看门狗定时器控制寄存器
}		
//t0设置
void hst0sz(void)
{
	AIC_IECR = set_12; //AIC中断使能命令寄存器
	TC0_CCR=0x01; // reset start软件触发命令软件触发执行：计数器复位，时钟启动
} 		
//中断设置
void hszdsz(void)
{
	AT91C_AIC_SVR[AT91C_ID_FIQ] = (uint32)irq_fiq;		//快速中断 0		
	AT91C_AIC_SVR[AT91C_ID_SYS] = (uint32)irq_SYS;
	AT91C_AIC_SVR[AT91C_ID_PIOA] = (uint32)irq_pioa;       //并行I/O控制器A  2
	AT91C_AIC_SVR[AT91C_ID_3_Reserved] = (uint32)irq_Reserved;     
	AT91C_AIC_SVR[AT91C_ID_ADC] = (uint32)irq_adc;         //模数转换器 4
	AT91C_AIC_SVR[AT91C_ID_SPI] = (uint32)irq_spi;        //串行外设接口 5
	AT91C_AIC_SVR[AT91C_ID_US0] = (uint32)irq_us0;        //USART 0 6
	AT91C_AIC_SVR[AT91C_ID_US1] = (uint32)irq_us1;        //USART 1 7
	AT91C_AIC_SVR[AT91C_ID_SSC] = (uint32)irq_ssc;         //同步串行接口 8
	AT91C_AIC_SVR[AT91C_ID_TWI] = (uint32)irq_twi;         //两线接口 9
	AT91C_AIC_SVR[AT91C_ID_PWMC] = (uint32)irq_pwmc;         //PWM 控制器 10
	AT91C_AIC_SVR[AT91C_ID_UDP] = (uint32)irq_udp;        //USB设备端口 11
	AT91C_AIC_SVR[AT91C_ID_TC0] = (uint32)irq_Tc0;         //定时器0中断	 12
	AT91C_AIC_SVR[AT91C_ID_TC1] = (uint32)irq_Tc1;         //定时器1中断	13
	AT91C_AIC_SVR[AT91C_ID_TC2] = (uint32)irq_Tc2;         //定时器2中断	14
	AT91C_AIC_SVR[AT91C_ID_15_Reserved] = (uint32)irq_15_Reserved;      
	AT91C_AIC_SVR[AT91C_ID_16_Reserved] = (uint32)irq_16_Reserved;        
	AT91C_AIC_SVR[AT91C_ID_17_Reserved] = (uint32)irq_17_Reserved;       
	AT91C_AIC_SVR[AT91C_ID_18_Reserved] = (uint32)irq_18_Reserved;         
	AT91C_AIC_SVR[AT91C_ID_19_Reserved] = (uint32)irq_19_Reserved;        
	AT91C_AIC_SVR[AT91C_ID_20_Reserved] = (uint32)irq_20_Reserved;
	AT91C_AIC_SVR[AT91C_ID_21_Reserved] = (uint32)irq_21_Reserved;
	AT91C_AIC_SVR[AT91C_ID_22_Reserved] = (uint32)irq_22_Reserved;
	AT91C_AIC_SVR[AT91C_ID_23_Reserved] = (uint32)irq_23_Reserved;
	AT91C_AIC_SVR[AT91C_ID_24_Reserved] = (uint32)irq_24_Reserved;
	AT91C_AIC_SVR[AT91C_ID_25_Reserved] = (uint32)irq_25_Reserved;
	AT91C_AIC_SVR[AT91C_ID_26_Reserved] = (uint32)irq_26_Reserved;
	AT91C_AIC_SVR[AT91C_ID_27_Reserved] = (uint32)irq_27_Reserved;
	AT91C_AIC_SVR[AT91C_ID_28_Reserved] = (uint32)irq_28_Reserved;
	AT91C_AIC_SVR[AT91C_ID_29_Reserved] = (uint32)irq_29_Reserved;
	AT91C_AIC_SVR[AT91C_ID_IRQ0] = (uint32)irq_IRQ0;
	AT91C_AIC_SVR[AT91C_ID_IRQ1] = (uint32)irq_IRQ1;
}
//io设置
void hsiosz(void)
{
		PIO_PER = 0xffffffff;		//使能寄存器，0 = 无效，1 = 使能（禁用引脚外设控制）。只写
		//PIO_PDR = 0xffffffff; 	//禁用寄存器，0 = 无效，1 = 禁用（使能引脚外设控制）。只写
		PIO_OER = 0xf;			//输出使能寄存器，0 = 无效，1 = 使能I/O 线上输出。只写
		PIO_OER |= set_8;
		PIO_OER |= set_9;
		PIO_OER |= set_10;
		PIO_OER |= set_24;		//PIO_OSR PIO 输出状态寄存器，0 = I/O 线为纯输入，1 = I/O 线输出使能。只读
		//PIO_IFER PIO 输入滤波器使能寄存器，0 = 无效，1 = 使能。只写
		//PIO_IFDR PIO 输入滤波器禁用寄存器，0 = 无效，1 = 禁用。只写
		//PIO_IFSR PIO 输入滤波器状态寄存器，0 = 滤波器禁用，1 = 滤波器使能。只读
		//PIO_SODR PIO 置位输出数据寄存器，0 = 无效，1 = 设置在I/O 线上驱动的数据。只写
		//PIO_CODR PIO 输出数据清零寄存器，0 = 无效，1 = 清除在I/O 线上驱动的数据。只写
		//PIO_ODSR PIO 输出数据状态寄存器，0 = 驱动到I/O线上的数据为0，1 = 驱动到I/O线上的数据为1。只读或读/写
		//PIO_PDSR PIO 引脚数据状态寄存器，0 = I/O线上的数据为0，1 = I/O线上的数据为1。只读
		//PIO_IER  = 0;	//PIO 中断使能寄存器，0 = 无效，1 = 使能I/O 线上输入变化中断。只写
		PIO_IDR = 0xffffffff;//中断禁用寄存器，0 = 无效，1 = 禁用I/O 线上输入变化中断。只写
		//PIO_IMR PIO 中断屏蔽寄存器，0 = I/O 线上输入变化中断禁用，1 = I/O 线上输入变化中断使能。只读
		//PIO_ISR PIO 中断状态寄存器，0 = 上次PIO_ISR读后或复位后， I/O 线上未检测到输入变化，1 = 上次PIO_ISR读后或复位后， I/O 线上至少检测到一次输入变化。只读
		PIO_MDER = 0xffffffff; 			//多驱动使能寄存器，0 = 无效，1 = 使能（使能引脚外设控制）。只写
		//PIO_MDDR PIO 多驱动禁用寄存器，0 = 无效，1 = 禁用（使能引脚外设控制）。只写
		//PIO_MDSR PIO 多驱动状态寄存器，0 = 禁用，引脚驱动为高低电平，1 = 使能，引脚仅驱动为低电平。只读
		//PIO_PUDR PIO 上拉禁用寄存器，0 = 无效，1 = 禁用I/O 线上拉电阻。只写
		PIO_PPUER = 0xffffffff;			//上拉使能寄存器，0 = 无效，1 = 使能I/O 线上拉电阻。只写
		//PIO_PUSR PIO 多驱动状态寄存器，0 = I/O 线上拉电阻使能，1 = I/O 线上拉电阻禁用。只读
		//PIO_ASR PIO 外设A 选择寄存器，0 = 无效，1 = I/O 线分配给外设A。只写
		//PIO_BSR PIO 外设B 选择寄存器，0 = 无效，1 = I/O 线分配给外设B。只写
		//PIO_ABSR PIO 外设A B 状态寄存器，0 = I/O 线分配给外设A，1 = I/O 线分配给外设B。只读
		PIO_OWER = 0xefffff8f;			//输出写使能寄存器，0 = 无效，1 = 使能I/O 线对PIO_ODSR 写。只写
		PIO_OWDR = 0x100000e0;//PIO //输出写禁用寄存器，0 = 无效，1 = 禁用I/O 线对PIO_ODSR 写。只写
		//PIO_OWSR PIO 输出写状态寄存器，0 = 写PIO_ODSR 不影响I/O 线，1 = 写PIO_ODSR 影响I/O 线。只读
}
//判断定时器
void hspdtc0()	
{
	//AIC_IDCR |= set_12; //AIC中断禁用命令寄存器
	if(uz_zd1msyd != 0)
	{
		uz_zd1msyd = 0;
		uz_1msyd = 1;	
	}
	//AIC_IECR |= set_12; //AIC中断使能命令寄存器
}
//清定时器
void hsqdsq()
{
	uz_1msyd = 0;
	uz_10msyd = 0;
	uz_100msyd = 0;
	uz_1syd = 0;
}			
//输入处理
unsigned char a0;
unsigned char a1;
unsigned char a2;
unsigned char a3;
void ws_hssrcl(unsigned long *ul_ccs,unsigned long *ul_srycz)
{
}	
//输出
void ws_hssc(void)
{
//	PIO_ODSR = ul_sc;
}
#define set_s PIO_SODR = set_8
#define clr_s PIO_CODR = set_8
#define set_cp1 PIO_SODR =  set_9
#define clr_cp1 PIO_CODR = set_9
#define set_cp2 PIO_SODR =  set_10
#define clr_cp2 PIO_CODR = set_10
#define set_disp PIO_SODR =  set_24
#define clr_disp PIO_CODR = set_24
//液晶驱动
void hsyjcl(void)
{
   unsigned char y;
   unsigned char jzsj;
   unsigned int jzsjdz;
   PIO_ODSR &= 0xfffffff0;
   jzsjdz = 0;
    clr_disp;
    {
		y = 239;
		set_disp;
		set_disp;
		set_disp;
		set_disp;
		set_disp;
		set_disp;
		set_disp;
		set_disp;
		set_disp;
		set_disp;
		set_disp;
		set_disp;
		set_disp;
		set_disp;
		set_disp;
		set_disp;
		clr_s; 
		clr_s;
		clr_s; 
		clr_s;
		clr_s; 
		clr_s;
		clr_s; 
		clr_s;
		set_cp1;
		set_cp1;
		set_cp1;
		set_cp1;
		set_cp1;
		set_cp1;
		set_cp1;
		set_cp1;
		set_s;
		set_s;
		set_s;
		set_s;
		set_s;
		set_s;
		set_s;
		set_s;
		set_s;
		set_s;
		set_s;
		set_s;
		set_s;
		set_s;
		set_s;
		set_s;
		clr_cp1;
		clr_cp1;
		clr_cp2;
		clr_cp2;
		clr_cp1;
		clr_cp1;
		clr_cp2;
		clr_cp2;
		clr_cp1;
		clr_cp1;
		clr_cp2;
		clr_cp2;
		clr_cp1;
		clr_cp1;
		clr_cp2;
		clr_cp2;
		clr_s;
		clr_s;
		while (y!=0)
		{ 
			hsqkmg();		//清看门狗
		    {  
		        PIO_ODSR &= 0xfffffff0; 
				jzsj = uc_yjsj[jzsjdz]; 
				jzsj = jzsj>>4;
				jzsj &= 0xf; 
				PIO_ODSR |= jzsj;
		        set_cp2; 
				set_cp2;
				set_cp2;
				set_cp2;
				set_cp2;
				set_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;//0
		        PIO_ODSR &= 0xfffffff0; 
				jzsj = uc_yjsj[jzsjdz]&0xf;
				++jzsjdz;  
				PIO_ODSR |= jzsj;  
		        set_cp2;
				set_cp2; 
		        set_cp2; 
				set_cp2;
				set_cp2;
				set_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2; //1
				PIO_ODSR &= 0xfffffff0; 
				jzsj = uc_yjsj[jzsjdz]; 
				jzsj = jzsj>>4;
				jzsj &= 0xf; 
				PIO_ODSR |= jzsj;
		        set_cp2; 
				set_cp2;
				set_cp2;
				set_cp2;
				set_cp2;
				set_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;//2
		        PIO_ODSR &= 0xfffffff0; 
				jzsj = uc_yjsj[jzsjdz]&0xf;
				++jzsjdz;  
				PIO_ODSR |= jzsj;  
		        set_cp2;
				set_cp2; 
		        set_cp2; 
				set_cp2;
				set_cp2;
				set_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2; //3
			    PIO_ODSR &= 0xfffffff0; 
				jzsj = uc_yjsj[jzsjdz]; 
				jzsj = jzsj>>4;
				jzsj &= 0xf; 
				PIO_ODSR |= jzsj;
		        set_cp2; 
				set_cp2;
				set_cp2;
				set_cp2;
				set_cp2;
				set_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;//4
		        PIO_ODSR &= 0xfffffff0; 
				jzsj = uc_yjsj[jzsjdz]&0xf;
				++jzsjdz;  
				PIO_ODSR |= jzsj;  
		        set_cp2;
				set_cp2; 
		        set_cp2; 
				set_cp2;
				set_cp2;
				set_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2; //5
			    PIO_ODSR &= 0xfffffff0; 
				jzsj = uc_yjsj[jzsjdz]; 
				jzsj = jzsj>>4;
				jzsj &= 0xf; 
				PIO_ODSR |= jzsj;
		        set_cp2; 
				set_cp2;
				set_cp2;
				set_cp2;
				set_cp2;
				set_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;//6
		        PIO_ODSR &= 0xfffffff0; 
				jzsj = uc_yjsj[jzsjdz]&0xf;
				++jzsjdz;  
				PIO_ODSR |= jzsj;  
		        set_cp2;
				set_cp2; 
		        set_cp2; 
				set_cp2;
				set_cp2;
				set_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2; //7
		        PIO_ODSR &= 0xfffffff0; 
				jzsj = uc_yjsj[jzsjdz]; 
				jzsj = jzsj>>4;
				jzsj &= 0xf; 
				PIO_ODSR |= jzsj;
		        set_cp2; 
				set_cp2;
				set_cp2;
				set_cp2;
				set_cp2;
				set_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;//8
		        PIO_ODSR &= 0xfffffff0; 
				jzsj = uc_yjsj[jzsjdz]&0xf;
				++jzsjdz;  
				PIO_ODSR |= jzsj;  
		        set_cp2;
				set_cp2; 
		        set_cp2; 
				set_cp2;
				set_cp2;
				set_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2; //9
		        PIO_ODSR &= 0xfffffff0; 
				jzsj = uc_yjsj[jzsjdz]; 
				jzsj = jzsj>>4;
				jzsj &= 0xf; 
				PIO_ODSR |= jzsj;
		        set_cp2; 
				set_cp2;
				set_cp2;
				set_cp2;
				set_cp2;
				set_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;//10
		        PIO_ODSR &= 0xfffffff0; 
				jzsj = uc_yjsj[jzsjdz]&0xf;
				++jzsjdz;  
				PIO_ODSR |= jzsj;  
		        set_cp2;
				set_cp2; 
		        set_cp2; 
				set_cp2;
				set_cp2;
				set_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2; //11
				PIO_ODSR &= 0xfffffff0; 
				jzsj = uc_yjsj[jzsjdz]; 
				jzsj = jzsj>>4;
				jzsj &= 0xf; 
				PIO_ODSR |= jzsj;
		        set_cp2; 
				set_cp2;
				set_cp2;
				set_cp2;
				set_cp2;
				set_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;//12
		        PIO_ODSR &= 0xfffffff0; 
				jzsj = uc_yjsj[jzsjdz]&0xf;
				++jzsjdz;  
				PIO_ODSR |= jzsj;  
		        set_cp2;
				set_cp2; 
		        set_cp2; 
				set_cp2;
				set_cp2;
				set_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2; //13
			    PIO_ODSR &= 0xfffffff0; 
				jzsj = uc_yjsj[jzsjdz]; 
				jzsj = jzsj>>4;
				jzsj &= 0xf; 
				PIO_ODSR |= jzsj;
		        set_cp2; 
				set_cp2;
				set_cp2;
				set_cp2;
				set_cp2;
				set_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;//14
		        PIO_ODSR &= 0xfffffff0; 
				jzsj = uc_yjsj[jzsjdz]&0xf;
				++jzsjdz;  
				PIO_ODSR |= jzsj;  
		        set_cp2;
				set_cp2; 
		        set_cp2; 
				set_cp2;
				set_cp2;
				set_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2; //15
			    PIO_ODSR &= 0xfffffff0; 
				jzsj = uc_yjsj[jzsjdz]; 
				jzsj = jzsj>>4;
				jzsj &= 0xf; 
				PIO_ODSR |= jzsj;
		        set_cp2; 
				set_cp2;
				set_cp2;
				set_cp2;
				set_cp2;
				set_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;
				clr_cp2;//16
		        PIO_ODSR &= 0xfffffff0; 
				jzsj = uc_yjsj[jzsjdz]&0xf;
				++jzsjdz;  
				PIO_ODSR |= jzsj;  
		        set_cp2;
				set_cp2; 
		        set_cp2;