myfx2.tan.qmsg

用于USB20芯片CY7C68013和FPGA之间的通信

{ "Info" "ITDB_FULL_TPD_RESULT" "PA\[1\] LED\[1\] 13.264 ns Longest " "Info: Longest tpd from source pin \"PA\[1\]\" to destination pin \"LED\[1\]\" is 13.264 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns PA\[1\] 1 PIN PIN_43 1 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_43; Fanout = 1; PIN Node = 'PA\[1\]'" {  } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/" "" "" { PA[1] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/MYFX2.v" 22 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(9.687 ns) + CELL(2.108 ns) 13.264 ns LED\[1\] 2 PIN PIN_181 0 " "Info: 2: + IC(9.687 ns) + CELL(2.108 ns) = 13.264 ns; Loc. = PIN_181; Fanout = 0; PIN Node = 'LED\[1\]'" {  } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/" "" "11.795 ns" { PA[1] LED[1] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/MYFX2.v" 34 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.577 ns 26.97 % " "Info: Total cell delay = 3.577 ns ( 26.97 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "9.687 ns 73.03 % " "Info: Total interconnect delay = 9.687 ns ( 73.03 % )" {  } {  } 0}  } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/" "" "13.264 ns" { PA[1] LED[1] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "13.264 ns" { PA[1] PA[1]~out0 LED[1] } { 0.000ns 0.000ns 9.687ns } { 0.000ns 1.469ns 2.108ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "LDT nRESET MMCLK 2.072 ns register " "Info: th for register \"LDT\" (data pin = \"nRESET\", clock pin = \"MMCLK\") is 2.072 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "MMCLK destination 5.762 ns + Longest register " "Info: + Longest clock path from clock \"MMCLK\" to destination register is 5.762 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns MMCLK 1 CLK PIN_153 24 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 24; CLK Node = 'MMCLK'" {  } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/" "" "" { MMCLK } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/MYFX2.v" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.069 ns) + CELL(0.935 ns) 4.473 ns Mega_cnt\[23\] 2 REG LC_X34_Y14_N6 2 " "Info: 2: + IC(2.069 ns) + CELL(0.935 ns) = 4.473 ns; Loc. = LC_X34_Y14_N6; Fanout = 2; REG Node = 'Mega_cnt\[23\]'" {  } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/" "" "3.004 ns" { MMCLK Mega_cnt[23] } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/MYFX2.v" 37 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.578 ns) + CELL(0.711 ns) 5.762 ns LDT 3 REG LC_X34_Y14_N9 2 " "Info: 3: + IC(0.578 ns) + CELL(0.711 ns) = 5.762 ns; Loc. = LC_X34_Y14_N9; Fanout = 2; REG Node = 'LDT'" {  } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/" "" "1.289 ns" { Mega_cnt[23] LDT } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns 54.06 % " "Info: Total cell delay = 3.115 ns ( 54.06 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.647 ns 45.94 % " "Info: Total interconnect delay = 2.647 ns ( 45.94 % )" {  } {  } 0}  } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/" "" "5.762 ns" { MMCLK Mega_cnt[23] LDT } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.762 ns" { MMCLK MMCLK~out0 Mega_cnt[23] LDT } { 0.000ns 0.000ns 2.069ns 0.578ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } {  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.705 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.705 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns nRESET 1 PIN PIN_29 25 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_29; Fanout = 25; PIN Node = 'nRESET'" {  } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/" "" "" { nRESET } "NODE_NAME" } "" } } { "MYFX2.v" "" { Text "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/MYFX2.v" 20 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.369 ns) + CELL(0.867 ns) 3.705 ns LDT 2 REG LC_X34_Y14_N9 2 " "Info: 2: + IC(1.369 ns) + CELL(0.867 ns) = 3.705 ns; Loc. = LC_X34_Y14_N9; Fanout = 2; REG Node = 'LDT'" {  } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/" "" "2.236 ns" { nRESET LDT } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.336 ns 63.05 % " "Info: Total cell delay = 2.336 ns ( 63.05 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.369 ns 36.95 % " "Info: Total interconnect delay = 1.369 ns ( 36.95 % )" {  } {  } 0}  } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/db/MYFX2_cmp.qrpt" Compiler "MYFX2" "UNKNOWN" "V1" "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/db/MYFX2.quartus_db" { Floorplan "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/" "" "3.705 ns" { nRESET LDT } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.705 ns" { nRESET nRESET~out0 LDT } { 0.000ns 0.000ns 1.369ns } { 0.000ns 1.469ns 0.867ns } } }  } 0}  } { { "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmware,Verilog代码）/USB2.0+FPGA_EXAMPLES/USB_FPGA_IO测试/FPGA代码/db/MYFX2_cmp.qrpt" "" { Report "G:/YCL-USB2.0-FPGA开发板V2.0/测试程序源代码（包括VC工程文件及Firmw