myfx2.tan.rpt

来自「用于USB20芯片CY7C68013和FPGA之间的通信」· RPT 代码 · 共 295 行 · 第 1/2 页

; N/A   ; None              ; 13.532 ns       ; RAMBD[10] ; GPD[10]   ;
; N/A   ; None              ; 13.482 ns       ; RAMBD[8]  ; GPD[8]    ;
; N/A   ; None              ; 13.415 ns       ; CTL[4]    ; GPD[6]    ;
; N/A   ; None              ; 13.393 ns       ; CTL[4]    ; GPD[5]    ;
; N/A   ; None              ; 13.329 ns       ; CTL[5]    ; GPD[0]    ;
; N/A   ; None              ; 13.269 ns       ; CTL[4]    ; GPD[7]    ;
; N/A   ; None              ; 13.254 ns       ; CTL[4]    ; RAMBD[2]  ;
; N/A   ; None              ; 13.177 ns       ; CTL[5]    ; GPD[2]    ;
; N/A   ; None              ; 13.169 ns       ; GPD[10]   ; RAMBD[10] ;
; N/A   ; None              ; 13.169 ns       ; CTL[5]    ; GPD[1]    ;
; N/A   ; None              ; 13.162 ns       ; RAMBD[5]  ; RAMBD[5]  ;
; N/A   ; None              ; 13.153 ns       ; RAMBD[11] ; GPD[11]   ;
; N/A   ; None              ; 13.108 ns       ; RAMBD[7]  ; RAMBD[7]  ;
; N/A   ; None              ; 13.100 ns       ; CTL[4]    ; RAMBD[3]  ;
; N/A   ; None              ; 13.099 ns       ; CTL[4]    ; RAMBD[8]  ;
; N/A   ; None              ; 13.094 ns       ; CTL[4]    ; GPD[4]    ;
; N/A   ; None              ; 13.067 ns       ; CTL[4]    ; RAMBD[10] ;
; N/A   ; None              ; 13.064 ns       ; GPD[1]    ; RAMBD[1]  ;
; N/A   ; None              ; 13.060 ns       ; RAMBD[6]  ; RAMBD[6]  ;
; N/A   ; None              ; 13.059 ns       ; CTL[4]    ; RAMBD[11] ;
; N/A   ; None              ; 13.012 ns       ; RAMBD[4]  ; GPD[4]    ;
; N/A   ; None              ; 13.012 ns       ; CTL[5]    ; GPD[3]    ;
; N/A   ; None              ; 12.919 ns       ; RAMBD[3]  ; GPD[3]    ;
; N/A   ; None              ; 12.916 ns       ; GPD[0]    ; RAMBD[0]  ;
; N/A   ; None              ; 12.883 ns       ; GPD[8]    ; RAMBD[8]  ;
; N/A   ; None              ; 12.879 ns       ; RAMBD[1]  ; GPD[1]    ;
; N/A   ; None              ; 12.848 ns       ; GPD[4]    ; RAMBD[4]  ;
; N/A   ; None              ; 12.822 ns       ; GPD[11]   ; RAMBD[11] ;
; N/A   ; None              ; 12.821 ns       ; CTL[4]    ; RAMBD[9]  ;
; N/A   ; None              ; 12.786 ns       ; GPD[2]    ; RAMBD[2]  ;
; N/A   ; None              ; 12.742 ns       ; GPD[3]    ; RAMBD[3]  ;
; N/A   ; None              ; 12.616 ns       ; RAMBD[0]  ; GPD[0]    ;
; N/A   ; None              ; 12.599 ns       ; RAMBD[2]  ; GPD[2]    ;
; N/A   ; None              ; 12.589 ns       ; RAMBD[6]  ; GPD[6]    ;
; N/A   ; None              ; 12.575 ns       ; GPD[6]    ; RAMBD[6]  ;
; N/A   ; None              ; 12.518 ns       ; GPD[5]    ; RAMBD[5]  ;
; N/A   ; None              ; 12.498 ns       ; RAMBD[7]  ; GPD[7]    ;
; N/A   ; None              ; 12.373 ns       ; RAMBD[5]  ; GPD[5]    ;
; N/A   ; None              ; 12.176 ns       ; CTL[4]    ; GPD[2]    ;
; N/A   ; None              ; 12.168 ns       ; CTL[4]    ; GPD[1]    ;
; N/A   ; None              ; 12.111 ns       ; RAMBD[9]  ; RAMBD[9]  ;
; N/A   ; None              ; 12.108 ns       ; GPD[7]    ; RAMBD[7]  ;
; N/A   ; None              ; 12.104 ns       ; GPD[6]    ; GPD[6]    ;
; N/A   ; None              ; 12.003 ns       ; CTL[4]    ; GPD[3]    ;
; N/A   ; None              ; 11.834 ns       ; CTL[4]    ; GPD[0]    ;
; N/A   ; None              ; 11.766 ns       ; GPD[4]    ; GPD[4]    ;
; N/A   ; None              ; 11.737 ns       ; RAMBD[10] ; RAMBD[10] ;
; N/A   ; None              ; 11.729 ns       ; GPD[5]    ; GPD[5]    ;
; N/A   ; None              ; 11.708 ns       ; GPD[2]    ; GPD[2]    ;
; N/A   ; None              ; 11.675 ns       ; RAMBD[8]  ; RAMBD[8]  ;
; N/A   ; None              ; 11.669 ns       ; GPA[8]    ; RAMBA[8]  ;
; N/A   ; None              ; 11.648 ns       ; GPD[1]    ; GPD[1]    ;
; N/A   ; None              ; 11.645 ns       ; GPD[3]    ; GPD[3]    ;
; N/A   ; None              ; 11.618 ns       ; CTL[4]    ; RAMBOE    ;
; N/A   ; None              ; 11.578 ns       ; CTL[5]    ; RAMBWE    ;
; N/A   ; None              ; 11.540 ns       ; RAMBD[11] ; RAMBD[11] ;
; N/A   ; None              ; 11.498 ns       ; GPD[7]    ; GPD[7]    ;
; N/A   ; None              ; 11.267 ns       ; GPA[3]    ; RAMBA[3]  ;
; N/A   ; None              ; 11.236 ns       ; GPA[4]    ; RAMBA[4]  ;
; N/A   ; None              ; 11.234 ns       ; GPA[2]    ; RAMBA[2]  ;
; N/A   ; None              ; 11.218 ns       ; GPA[1]    ; RAMBA[1]  ;
; N/A   ; None              ; 11.195 ns       ; GPA[0]    ; RAMBA[0]  ;
; N/A   ; None              ; 11.170 ns       ; GPD[0]    ; GPD[0]    ;
; N/A   ; None              ; 10.755 ns       ; CTL[3]    ; RAMBCE    ;
; N/A   ; None              ; 10.605 ns       ; GPA[6]    ; RAMBA[6]  ;
; N/A   ; None              ; 10.583 ns       ; PA[0]     ; RAMBA[9]  ;
; N/A   ; None              ; 10.563 ns       ; GPA[7]    ; RAMBA[7]  ;
; N/A   ; None              ; 10.529 ns       ; GPA[5]    ; RAMBA[5]  ;
; N/A   ; None              ; 10.246 ns       ; PA[5]     ; RAMBA[14] ;
; N/A   ; None              ; 9.974 ns        ; PA[4]     ; RAMBA[13] ;
; N/A   ; None              ; 9.949 ns        ; PA[3]     ; RAMBA[12] ;
; N/A   ; None              ; 9.868 ns        ; PA[2]     ; RAMBA[11] ;
; N/A   ; None              ; 9.857 ns        ; PA[1]     ; RAMBA[10] ;
+-------+-------------------+-----------------+-----------+-----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Tue Feb 06 19:41:51 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off MYFX2 -c MYFX2 --timing_analysis_only
Warning: Timing Analysis found one or more latches implemented as combinational loops
    Warning: Node "DREG[0]" is a latch
    Warning: Node "DREG[1]" is a latch
    Warning: Node "DREG[2]" is a latch
    Warning: Node "DREG[3]" is a latch
    Warning: Node "DREG[4]" is a latch
    Warning: Node "DREG[5]" is a latch
    Warning: Node "DREG[6]" is a latch
    Warning: Node "DREG[7]" is a latch
    Warning: Node "DREG[8]" is a latch
    Warning: Node "DREG[9]" is a latch
    Warning: Node "DREG[10]" is a latch
    Warning: Node "DREG[11]" is a latch
    Warning: Node "DREG[12]" is a latch
    Warning: Node "DREG[13]" is a latch
    Warning: Node "DREG[14]" is a latch
    Warning: Node "DREG[15]" is a latch
Info: Found combinational loop of 1 nodes
    Info: Node "DREG[15]"
Info: Found combinational loop of 1 nodes
    Info: Node "DREG[14]"
Info: Found combinational loop of 1 nodes
    Info: Node "DREG[13]"
Info: Found combinational loop of 1 nodes
    Info: Node "DREG[12]"
Info: Found combinational loop of 1 nodes
    Info: Node "DREG[11]"
Info: Found combinational loop of 1 nodes
    Info: Node "DREG[10]"
Info: Found combinational loop of 1 nodes
    Info: Node "DREG[9]"
Info: Found combinational loop of 1 nodes
    Info: Node "DREG[8]"
Info: Found combinational loop of 1 nodes
    Info: Node "DREG[7]"
Info: Found combinational loop of 1 nodes
    Info: Node "DREG[6]"
Info: Found combinational loop of 1 nodes
    Info: Node "DREG[5]"
Info: Found combinational loop of 1 nodes
    Info: Node "DREG[4]"
Info: Found combinational loop of 1 nodes
    Info: Node "DREG[3]"
Info: Found combinational loop of 1 nodes
    Info: Node "DREG[2]"
Info: Found combinational loop of 1 nodes
    Info: Node "DREG[1]"
Info: Found combinational loop of 1 nodes
    Info: Node "DREG[0]"
Info: Longest tpd from source pin "CTL[5]" to destination pin "GPD[12]" is 16.239 ns
    Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_20; Fanout = 34; PIN Node = 'CTL[5]'
    Info: 2: + IC(7.006 ns) + CELL(0.114 ns) = 8.589 ns; Loc. = LC_X6_Y1_N0; Fanout = 32; COMB Node = 'DREG~72'
    Info: 3: + IC(0.000 ns) + CELL(1.746 ns) = 10.335 ns; Loc. = LC_X7_Y2_N4; Fanout = 3; COMB LOOP Node = 'DREG[12]'
        Info: Loc. = LC_X7_Y2_N4; Node "DREG[12]"
    Info: 4: + IC(3.780 ns) + CELL(2.124 ns) = 16.239 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'GPD[12]'
    Info: Total cell delay = 5.453 ns ( 33.58 % )
    Info: Total interconnect delay = 10.786 ns ( 66.42 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 17 warnings
    Info: Processing ended: Tue Feb 06 19:41:52 2007
    Info: Elapsed time: 00:00:02