myfx2.tan.rpt

用于USB20芯片CY7C68013和FPGA之间的通信

; N/A   ; None         ; 15.916 ns  ; RDY[1]~reg0 ; RDY[1]  ; MMCLK      ;
; N/A   ; None         ; 15.840 ns  ; DREG[5]     ; GPD[5]  ; MMCLK      ;
; N/A   ; None         ; 15.774 ns  ; RDY[1]~reg0 ; GPD[2]  ; MMCLK      ;
; N/A   ; None         ; 15.774 ns  ; RDY[1]~reg0 ; GPD[1]  ; MMCLK      ;
; N/A   ; None         ; 15.770 ns  ; DREG[3]     ; GPD[3]  ; MMCLK      ;
; N/A   ; None         ; 15.765 ns  ; DREG[2]     ; GPD[2]  ; MMCLK      ;
; N/A   ; None         ; 15.761 ns  ; RDY[1]~reg0 ; GPD[3]  ; MMCLK      ;
; N/A   ; None         ; 15.672 ns  ; DREG[10]    ; GPD[10] ; MMCLK      ;
; N/A   ; None         ; 15.664 ns  ; DREG[9]     ; GPD[9]  ; MMCLK      ;
; N/A   ; None         ; 15.654 ns  ; DREG[11]    ; GPD[11] ; MMCLK      ;
; N/A   ; None         ; 15.556 ns  ; RDY[1]~reg0 ; GPD[15] ; MMCLK      ;
; N/A   ; None         ; 15.556 ns  ; RDY[1]~reg0 ; GPD[14] ; MMCLK      ;
; N/A   ; None         ; 15.205 ns  ; DREG[8]     ; GPD[8]  ; MMCLK      ;
; N/A   ; None         ; 15.203 ns  ; RDY[1]~reg0 ; GPD[13] ; MMCLK      ;
; N/A   ; None         ; 15.203 ns  ; RDY[1]~reg0 ; GPD[12] ; MMCLK      ;
; N/A   ; None         ; 15.182 ns  ; RDY[1]~reg0 ; GPD[11] ; MMCLK      ;
; N/A   ; None         ; 15.044 ns  ; RDY[1]~reg0 ; GPD[8]  ; MMCLK      ;
; N/A   ; None         ; 14.719 ns  ; RDY[1]~reg0 ; GPD[10] ; MMCLK      ;
; N/A   ; None         ; 14.719 ns  ; RDY[1]~reg0 ; GPD[9]  ; MMCLK      ;
+-------+--------------+------------+-------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Tue Feb 06 20:37:53 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off MYFX2 -c MYFX2 --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "MMCLK" is an undefined clock
Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "CLK_2" as buffer
    Info: Detected ripple clock "CLK_4" as buffer
    Info: Detected ripple clock "CLK_8" as buffer
Info: Clock "MMCLK" Internal fmax is restricted to 275.03 MHz between source register "DREG[9]" and destination register "DREG[15]"
    Info: fmax restricted to Clock High delay (1.818 ns) plus Clock Low delay (1.818 ns) : restricted to 3.636 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 2.266 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X2_Y14_N1; Fanout = 4; REG Node = 'DREG[9]'
            Info: 2: + IC(0.529 ns) + CELL(0.564 ns) = 1.093 ns; Loc. = LC_X2_Y14_N1; Fanout = 2; COMB Node = 'DREG[9]~165'
            Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 1.171 ns; Loc. = LC_X2_Y14_N2; Fanout = 2; COMB Node = 'DREG[10]~169'
            Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 1.249 ns; Loc. = LC_X2_Y14_N3; Fanout = 2; COMB Node = 'DREG[11]~173'
            Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 1.427 ns; Loc. = LC_X2_Y14_N4; Fanout = 3; COMB Node = 'DREG[12]~177'
            Info: 6: + IC(0.000 ns) + CELL(0.839 ns) = 2.266 ns; Loc. = LC_X2_Y14_N7; Fanout = 2; REG Node = 'DREG[15]'
            Info: Total cell delay = 1.737 ns ( 76.65 % )
            Info: Total interconnect delay = 0.529 ns ( 23.35 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "MMCLK" to destination register is 11.452 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 1; CLK Node = 'MMCLK'
                Info: 2: + IC(3.358 ns) + CELL(0.935 ns) = 5.762 ns; Loc. = LC_X3_Y14_N2; Fanout = 2; REG Node = 'CLK_2'
                Info: 3: + IC(0.567 ns) + CELL(0.935 ns) = 7.264 ns; Loc. = LC_X3_Y14_N4; Fanout = 2; REG Node = 'CLK_4'
                Info: 4: + IC(1.285 ns) + CELL(0.935 ns) = 9.484 ns; Loc. = LC_X3_Y15_N6; Fanout = 20; REG Node = 'CLK_8'
                Info: 5: + IC(1.257 ns) + CELL(0.711 ns) = 11.452 ns; Loc. = LC_X2_Y14_N7; Fanout = 2; REG Node = 'DREG[15]'
                Info: Total cell delay = 4.985 ns ( 43.53 % )
                Info: Total interconnect delay = 6.467 ns ( 56.47 % )
            Info: - Longest clock path from clock "MMCLK" to source register is 11.452 ns
                Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 1; CLK Node = 'MMCLK'
                Info: 2: + IC(3.358 ns) + CELL(0.935 ns) = 5.762 ns; Loc. = LC_X3_Y14_N2; Fanout = 2; REG Node = 'CLK_2'
                Info: 3: + IC(0.567 ns) + CELL(0.935 ns) = 7.264 ns; Loc. = LC_X3_Y14_N4; Fanout = 2; REG Node = 'CLK_4'
                Info: 4: + IC(1.285 ns) + CELL(0.935 ns) = 9.484 ns; Loc. = LC_X3_Y15_N6; Fanout = 20; REG Node = 'CLK_8'
                Info: 5: + IC(1.257 ns) + CELL(0.711 ns) = 11.452 ns; Loc. = LC_X2_Y14_N1; Fanout = 4; REG Node = 'DREG[9]'
                Info: Total cell delay = 4.985 ns ( 43.53 % )
                Info: Total interconnect delay = 6.467 ns ( 56.47 % )
        Info: + Micro clock to output delay of source is 0.224 ns
        Info: + Micro setup delay of destination is 0.037 ns
Info: tco from clock "MMCLK" to destination pin "GPD[5]" through register "RDY[1]~reg0" is 16.410 ns
    Info: + Longest clock path from clock "MMCLK" to source register is 10.766 ns
        Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_153; Fanout = 1; CLK Node = 'MMCLK'
        Info: 2: + IC(3.358 ns) + CELL(0.935 ns) = 5.762 ns; Loc. = LC_X3_Y14_N2; Fanout = 2; REG Node = 'CLK_2'
        Info: 3: + IC(0.567 ns) + CELL(0.935 ns) = 7.264 ns; Loc. = LC_X3_Y14_N4; Fanout = 2; REG Node = 'CLK_4'
        Info: 4: + IC(1.285 ns) + CELL(0.935 ns) = 9.484 ns; Loc. = LC_X3_Y15_N6; Fanout = 20; REG Node = 'CLK_8'
        Info: 5: + IC(0.571 ns) + CELL(0.711 ns) = 10.766 ns; Loc. = LC_X3_Y15_N5; Fanout = 18; REG Node = 'RDY[1]~reg0'
        Info: Total cell delay = 4.985 ns ( 46.30 % )
        Info: Total interconnect delay = 5.781 ns ( 53.70 % )
    Info: + Micro clock to output delay of source is 0.224 ns
    Info: + Longest register to pin delay is 5.420 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y15_N5; Fanout = 18; REG Node = 'RDY[1]~reg0'
        Info: 2: + IC(3.341 ns) + CELL(2.079 ns) = 5.420 ns; Loc. = PIN_62; Fanout = 0; PIN Node = 'GPD[5]'
        Info: Total cell delay = 2.079 ns ( 38.36 % )
        Info: Total interconnect delay = 3.341 ns ( 61.64 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Tue Feb 06 20:37:55 2007
    Info: Elapsed time: 00:00:04