correlate_and_accumulate.par

如何使用ISE和FPGA使用指南

INST "wr_clk_chd_core/BUFR_div8_inst" LOC = "BUFR_X0Y6" ;
NET "wr_clk_chd_bufr_div8" TNM_NET = "TN_wr_clk_chd_bufr_div8" ;
TIMEGRP "TN_wr_clk_chd_bufr_div8" AREA_GROUP = "CLKAG_wr_clk_chd_bufr_div8" ;
AREA_GROUP "CLKAG_wr_clk_chd_bufr_div8" RANGE = CLOCKREGION_X0Y3;


# Regional-Clock "wr_clk_chc_bufr_div8" driven by "BUFR_X0Y5"
INST "wr_clk_chc_core/BUFR_div8_inst" LOC = "BUFR_X0Y5" ;
NET "wr_clk_chc_bufr_div8" TNM_NET = "TN_wr_clk_chc_bufr_div8" ;
TIMEGRP "TN_wr_clk_chc_bufr_div8" AREA_GROUP = "CLKAG_wr_clk_chc_bufr_div8" ;
AREA_GROUP "CLKAG_wr_clk_chc_bufr_div8" RANGE = CLOCKREGION_X0Y2, CLOCKREGION_X0Y1;


# Regional-Clock "wr_clk_chc_bufr" driven by "BUFR_X0Y4"
INST "wr_clk_chc_core/BUFR_inst" LOC = "BUFR_X0Y4" ;
NET "wr_clk_chc_bufr" TNM_NET = "TN_wr_clk_chc_bufr" ;
TIMEGRP "TN_wr_clk_chc_bufr" AREA_GROUP = "CLKAG_wr_clk_chc_bufr" ;
AREA_GROUP "CLKAG_wr_clk_chc_bufr" RANGE = CLOCKREGION_X0Y2, CLOCKREGION_X0Y1;


# Regional-Clock "wr_clk_chb_bufr" driven by "BUFR_X1Y7"
INST "wr_clk_chb_core/BUFR_inst" LOC = "BUFR_X1Y7" ;
NET "wr_clk_chb_bufr" TNM_NET = "TN_wr_clk_chb_bufr" ;
TIMEGRP "TN_wr_clk_chb_bufr" AREA_GROUP = "CLKAG_wr_clk_chb_bufr" ;
AREA_GROUP "CLKAG_wr_clk_chb_bufr" RANGE = CLOCKREGION_X1Y3;


# Regional-Clock "wr_clk_chb_bufr_div8" driven by "BUFR_X1Y6"
INST "wr_clk_chb_core/BUFR_div8_inst" LOC = "BUFR_X1Y6" ;
NET "wr_clk_chb_bufr_div8" TNM_NET = "TN_wr_clk_chb_bufr_div8" ;
TIMEGRP "TN_wr_clk_chb_bufr_div8" AREA_GROUP = "CLKAG_wr_clk_chb_bufr_div8" ;
AREA_GROUP "CLKAG_wr_clk_chb_bufr_div8" RANGE = CLOCKREGION_X1Y3;


# Regional-Clock "wr_clk_cha_bufr_div8" driven by "BUFR_X1Y4"
INST "wr_clk_cha_core/BUFR_div8_inst" LOC = "BUFR_X1Y4" ;
NET "wr_clk_cha_bufr_div8" TNM_NET = "TN_wr_clk_cha_bufr_div8" ;
TIMEGRP "TN_wr_clk_cha_bufr_div8" AREA_GROUP = "CLKAG_wr_clk_cha_bufr_div8" ;
AREA_GROUP "CLKAG_wr_clk_cha_bufr_div8" RANGE = CLOCKREGION_X1Y2, CLOCKREGION_X1Y1;


# Regional-Clock "wr_clk_cha_bufr" driven by "BUFR_X1Y5"
INST "wr_clk_cha_core/BUFR_inst" LOC = "BUFR_X1Y5" ;
NET "wr_clk_cha_bufr" TNM_NET = "TN_wr_clk_cha_bufr" ;
TIMEGRP "TN_wr_clk_cha_bufr" AREA_GROUP = "CLKAG_wr_clk_cha_bufr" ;
AREA_GROUP "CLKAG_wr_clk_cha_bufr" RANGE = CLOCKREGION_X1Y2, CLOCKREGION_X1Y1;



Phase 4.2 (Checksum:26259fc) REAL time: 11 secs 

Phase 5.30
Phase 5.30 (Checksum:2faf07b) REAL time: 11 secs 

Phase 6.3
Phase 6.3 (Checksum:39386fa) REAL time: 11 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 11 secs 

Phase 8.8
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.............................................................................................
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Phase 8.8 (Checksum:b75a77) REAL time: 19 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 20 secs 

Phase 11.18
Phase 11.18 (Checksum:68e7775) REAL time: 26 secs 

Phase 12.27
Phase 12.27 (Checksum:7270df4) REAL time: 26 secs 

Phase 13.5
Phase 13.5 (Checksum:7bfa473) REAL time: 26 secs 

REAL time consumed by placer: 27 secs 
CPU  time consumed by placer: 26 secs 
Writing design to file correlate_and_accumulate.ncd


Total REAL time to Placer completion: 28 secs 
Total CPU time to Placer completion: 27 secs 

Starting Router

Phase 1: 3608 unrouted;       REAL time: 29 secs 

Phase 2: 2914 unrouted;       REAL time: 29 secs 

Phase 3: 991 unrouted;       REAL time: 30 secs 

Phase 4: 991 unrouted; (36718)      REAL time: 30 secs 

Phase 5: 1034 unrouted; (0)      REAL time: 30 secs 

Phase 6: 0 unrouted; (0)      REAL time: 31 secs 

Phase 7: 0 unrouted; (0)      REAL time: 32 secs 

Phase 8: 0 unrouted; (0)      REAL time: 32 secs 

Phase 9: 0 unrouted; (0)      REAL time: 32 secs 

Phase 10: 0 unrouted; (0)      REAL time: 32 secs 

Total REAL time to Router completion: 32 secs 
Total CPU time to Router completion: 31 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|         rd_clk_bufg | BUFGCTRL_X0Y0| No   |  212 |  0.209     |  2.031      |
+---------------------+--------------+------+------+------------+-------------+
|    wr_clk_chd_bufio |        IO Clk| No   |    4 |  0.000     |  0.658      |
+---------------------+--------------+------+------+------------+-------------+
|wr_clk_chd_bufr_div8 |              |      |      |            |             |
|                     |  Regional Clk| No   |    2 |  0.000     |  0.444      |
+---------------------+--------------+------+------+------------+-------------+
|     wr_clk_chd_bufr |  Regional Clk| No   |   24 |  0.066     |  0.464      |
+---------------------+--------------+------+------+------------+-------------+
|    wr_clk_chc_bufio |        IO Clk| No   |    4 |  0.000     |  0.662      |
+---------------------+--------------+------+------+------------+-------------+
|wr_clk_chc_bufr_div8 |              |      |      |            |             |
|                     |  Regional Clk| No   |    2 |  0.000     |  0.463      |
+---------------------+--------------+------+------+------------+-------------+
|     wr_clk_chc_bufr |  Regional Clk| No   |   24 |  0.038     |  0.516      |
+---------------------+--------------+------+------+------------+-------------+
|    wr_clk_chb_bufio |        IO Clk| No   |    4 |  0.000     |  0.658      |
+---------------------+--------------+------+------+------------+-------------+
|wr_clk_chb_bufr_div8 |              |      |      |            |             |
|                     |  Regional Clk| No   |    2 |  0.000     |  0.438      |
+---------------------+--------------+------+------+------------+-------------+
|     wr_clk_chb_bufr |  Regional Clk| No   |   24 |  0.049     |  0.469      |
+---------------------+--------------+------+------+------------+-------------+
|    wr_clk_cha_bufio |        IO Clk| No   |    4 |  0.000     |  0.662      |
+---------------------+--------------+------+------+------------+-------------+
|wr_clk_cha_bufr_div8 |              |      |      |            |             |
|                     |  Regional Clk| No   |    2 |  0.000     |  0.457      |
+---------------------+--------------+------+------+------------+-------------+
|     wr_clk_cha_bufr |  Regional Clk| No   |   24 |  0.056     |  0.507      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.


   The Delay Summary Report


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        0.836
   The MAXIMUM PIN DELAY IS:                               4.011
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.147

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 5.00  d >= 5.00
   ---------   ---------   ---------   ---------   ---------   ---------
        2452         662         143          67           1           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing   
                                            |         |    Slack   | Achievable | Errors |    Score   
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net rd_ | SETUP   |         N/A|     3.694ns|     N/A|           0
  clk_bufg                                  | HOLD    |     0.379ns|            |       0|           0
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net wr_ | SETUP   |         N/A|     3.217ns|     N/A|           0
  clk_chd_bufr                              | HOLD    |     0.338ns|            |       0|           0
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net wr_ | SETUP   |         N/A|     3.174ns|     N/A|           0
  clk_chc_bufr                              | HOLD    |     0.387ns|            |       0|           0
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net wr_ | SETUP   |         N/A|     3.114ns|     N/A|           0
  clk_chb_bufr                              | HOLD    |     0.382ns|            |       0|           0
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net wr_ | SETUP   |         N/A|     3.476ns|     N/A|           0
  clk_cha_bufr                              | HOLD    |     0.407ns|            |       0|           0
------------------------------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the 
   constraint does not cover any paths or that it has no requested value.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 51 secs 
Total CPU time to PAR completion: 33 secs 

Peak Memory Usage:  237 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file correlate_and_accumulate.ncd



PAR done!