correlate_and_accumulate.par

如何使用ISE和FPGA使用指南

Release 9.1.01i par J.31
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

SJC-XILISTG1::  Fri Apr 06 14:05:59 2007

par -w -intstyle ise -ol std -t 1 correlate_and_accumulate_map.ncd
correlate_and_accumulate.ncd correlate_and_accumulate.pcf 


Constraints file: correlate_and_accumulate.pcf.
Loading device for application Rf_Device from file '4vlx15.nph' in environment Y:\XILI\FISE_9_1i_SP1.
   "correlate_and_accumulate" is an NCD, version 3.1, device xc4vlx15, package sf363, speed -12
This design is using the default stepping level (major silicon revision) for this device (1). Unless your design is
targeted at devices of this stepping level, it is recommended that you explicitly specify the stepping level of the
parts you will be using. This will allow the tools to take advantage of any available performance and functional
enhancements for this device. The latest stepping level for this device is '2'. Additional information on "stepping
level" is available at support.xilinx.com.

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
   the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high". For a
   balance between the fastest runtime and best performance, set the effort level to "med".

Device speed data version:  "PRODUCTION 1.63 2006-12-13".


Device Utilization Summary:

   Number of BUFGs                           1 out of 32      3%
   Number of BUFIOs                          4 out of 24     16%
   Number of BUFRs                           8 out of 16     50%
   Number of DCM_ADVs                        1 out of 4      25%
   Number of DSP48s                          4 out of 32     12%
   Number of FIFO16s                         4 out of 48      8%
   Number of External IOBs                 110 out of 240    45%
      Number of LOCed IOBs                 110 out of 110   100%

   Number of ISERDESs                        8 out of 320     2%
   Number of OLOGICs                        84 out of 320    26%
   Number of Slices                        403 out of 6144    6%
      Number of SLICEMs                      0 out of 3072    0%



Overall effort level (-ol):   Standard 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard 


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:98afb7) REAL time: 10 secs 

Phase 2.7
Phase 2.7 (Checksum:1312cfe) REAL time: 10 secs 

Phase 3.31
Phase 3.31 (Checksum:1c9c37d) REAL time: 10 secs 

Phase 4.2
......


There are 8 clock regions on the target FPGA device:
|------------------------------------------|------------------------------------------|
| CLOCKREGION_X0Y3:                        | CLOCKREGION_X1Y3:                        |
|   2 BUFRs available, 2 in use            |   2 BUFRs available, 2 in use            |
|   2 Regional Clock Spines, 2 in use      |   2 Regional Clock Spines, 2 in use      |
|   2 edge BUFIOs available, 1 in use      |   2 edge BUFIOs available, 1 in use      |
|   2 center BUFIOs available, 0 in use    |                                          |
|                                          |                                          |
|------------------------------------------|------------------------------------------|
| CLOCKREGION_X0Y2:                        | CLOCKREGION_X1Y2:                        |
|   2 BUFRs available, 2 in use            |   2 BUFRs available, 2 in use            |
|   2 Regional Clock Spines, 2 in use      |   2 Regional Clock Spines, 2 in use      |
|   2 edge BUFIOs available, 1 in use      |   2 edge BUFIOs available, 1 in use      |
|   2 center BUFIOs available, 0 in use    |                                          |
|                                          |                                          |
|------------------------------------------|------------------------------------------|
| CLOCKREGION_X0Y1:                        | CLOCKREGION_X1Y1:                        |
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
|   2 Regional Clock Spines, 2 in use      |   2 Regional Clock Spines, 2 in use      |
|   2 edge BUFIOs available, 0 in use      |   2 edge BUFIOs available, 0 in use      |
|   2 center BUFIOs available, 0 in use    |                                          |
|                                          |                                          |
|------------------------------------------|------------------------------------------|
| CLOCKREGION_X0Y0:                        | CLOCKREGION_X1Y0:                        |
|   2 BUFRs available, 0 in use            |   2 BUFRs available, 0 in use            |
|   2 Regional Clock Spines, 0 in use      |   2 Regional Clock Spines, 0 in use      |
|   2 edge BUFIOs available, 0 in use      |   2 edge BUFIOs available, 0 in use      |
|   2 center BUFIOs available, 0 in use    |                                          |
|                                          |                                          |
|------------------------------------------|------------------------------------------|


Clock-Region: <CLOCKREGION_X0Y2>
  key resource utilizations (used/available): edge-bufios - 1/2; center-bufios - 0/2; bufrs - 2/2; regional-clock-spines - 2/2
|-----------------------------------------------------------------------------------------------------------------------------------------------------
|       |    clock    | BRAM |     |    |        |        |        |        |      |      |     |      |
|       |    region   | FIFO | DCM | GT | ILOGIC | OLOGIC | SLICEM | SLICEL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)
|-------|-------------|------|-----|----|--------|--------|--------|--------|------|------|-----|------|----------------------------------------------
|       | Upper Region|   4  |  2  |  0 |   48   |   48   |    384 |    384 |   8  |   0  |  0  |   0  | <- Available resources in the upper region
|-------|-------------|------|-----|----|--------|--------|--------|--------|------|------|-----|------|----------------------------------------------
|       |CurrentRegion|   4  |  0  |  0 |   48   |   48   |    384 |    384 |   8  |   0  |  0  |   0  | <- Available resources in this current region
|-------|-------------|------|-----|----|--------|--------|--------|--------|------|------|-----|------|----------------------------------------------
|       | Lower Region|   4  |  0  |  0 |   48   |   48   |    384 |    384 |   8  |   0  |  0  |   0  | <- Available resources in the lower region
|-------|-------------|------|-----|----|--------|--------|--------|--------|------|------|-----|------|----------------------------------------------
| clock |    region   |                                                                                -----------------------------------------------
|  type |  expansion  |                                                                                | <IO/Regional clock Net Name>
|-------|-------------|------|-----|----|--------|--------|--------|--------|------|------|-----|------|----------------------------------------------
| BUFIO |             |   0  |  0  |  0 |    2   |    0   |      0 |      0 |   0  |   0  |  0  |   0  | "wr_clk_chc_bufio"
|-------|-------------|------|-----|----|--------|--------|--------|--------|------|------|-----|------|----------------------------------------------
|  BUFR |       Lower |   0  |  0  |  0 |    2   |    0   |      0 |      0 |   0  |   0  |  0  |   0  | "wr_clk_chc_bufr_div8"
|-------|-------------|------|-----|----|--------|--------|--------|--------|------|------|-----|------|----------------------------------------------
|  BUFR |       Lower |   1  |  0  |  0 |    0   |    0   |      0 |     23 |   0  |   0  |  0  |   0  | "wr_clk_chc_bufr"
|-------|-------------|------|-----|----|--------|--------|--------|--------|------|------|-----|------|----------------------------------------------


Clock-Region: <CLOCKREGION_X1Y2>
  key resource utilizations (used/available): edge-bufios - 1/2; bufrs - 2/2; regional-clock-spines - 2/2
|-----------------------------------------------------------------------------------------------------------------------------------------------------
|       |    clock    | BRAM |     |    |        |        |        |        |      |      |     |      |
|       |    region   | FIFO | DCM | GT | ILOGIC | OLOGIC | SLICEM | SLICEL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)
|-------|-------------|------|-----|----|--------|--------|--------|--------|------|------|-----|------|----------------------------------------------
|       | Upper Region|   8  |  0  |  0 |   32   |   32   |    384 |    384 |   0  |   0  |  0  |   0  | <- Available resources in the upper region
|-------|-------------|------|-----|----|--------|--------|--------|--------|------|------|-----|------|----------------------------------------------
|       |CurrentRegion|   8  |  0  |  0 |   32   |   32   |    384 |    384 |   0  |   0  |  0  |   0  | <- Available resources in this current region
|-------|-------------|------|-----|----|--------|--------|--------|--------|------|------|-----|------|----------------------------------------------
|       | Lower Region|   8  |  0  |  0 |   32   |   32   |    384 |    384 |   0  |   0  |  0  |   0  | <- Available resources in the lower region
|-------|-------------|------|-----|----|--------|--------|--------|--------|------|------|-----|------|----------------------------------------------
| clock |    region   |                                                                                -----------------------------------------------
|  type |  expansion  |                                                                                | <IO/Regional clock Net Name>
|-------|-------------|------|-----|----|--------|--------|--------|--------|------|------|-----|------|----------------------------------------------
| BUFIO |             |   0  |  0  |  0 |    2   |    0   |      0 |      0 |   0  |   0  |  0  |   0  | "wr_clk_cha_bufio"
|-------|-------------|------|-----|----|--------|--------|--------|--------|------|------|-----|------|----------------------------------------------
|  BUFR |       Lower |   0  |  0  |  0 |    2   |    0   |      0 |      0 |   0  |   0  |  0  |   0  | "wr_clk_cha_bufr_div8"
|-------|-------------|------|-----|----|--------|--------|--------|--------|------|------|-----|------|----------------------------------------------
|  BUFR |       Lower |   1  |  0  |  0 |    0   |    0   |      0 |     23 |   0  |   0  |  0  |   0  | "wr_clk_cha_bufr"
|-------|-------------|------|-----|----|--------|--------|--------|--------|------|------|-----|------|----------------------------------------------


Clock-Region: <CLOCKREGION_X0Y3>
  key resource utilizations (used/available): edge-bufios - 1/2; center-bufios - 0/2; bufrs - 2/2; regional-clock-spines - 2/2
|-----------------------------------------------------------------------------------------------------------------------------------------------------
|       |    clock    | BRAM |     |    |        |        |        |        |      |      |     |      |
|       |    region   | FIFO | DCM | GT | ILOGIC | OLOGIC | SLICEM | SLICEL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)
|-------|-------------|------|-----|----|--------|--------|--------|--------|------|------|-----|------|----------------------------------------------
|       |CurrentRegion|   4  |  2  |  0 |   48   |   48   |    384 |    384 |   8  |   0  |  0  |   0  | <- Available resources in this current region
|-------|-------------|------|-----|----|--------|--------|--------|--------|------|------|-----|------|----------------------------------------------
|       | Lower Region|   4  |  0  |  0 |   48   |   48   |    384 |    384 |   8  |   0  |  0  |   0  | <- Available resources in the lower region
|-------|-------------|------|-----|----|--------|--------|--------|--------|------|------|-----|------|----------------------------------------------
| clock |    region   |                                                                                -----------------------------------------------
|  type |  expansion  |                                                                                | <IO/Regional clock Net Name>
|-------|-------------|------|-----|----|--------|--------|--------|--------|------|------|-----|------|----------------------------------------------
| BUFIO |             |   0  |  0  |  0 |    2   |    0   |      0 |      0 |   0  |   0  |  0  |   0  | "wr_clk_chd_bufio"
|-------|-------------|------|-----|----|--------|--------|--------|--------|------|------|-----|------|----------------------------------------------
|  BUFR |             |   1  |  0  |  0 |    0   |    0   |      0 |     23 |   0  |   0  |  0  |   0  | "wr_clk_chd_bufr"
|-------|-------------|------|-----|----|--------|--------|--------|--------|------|------|-----|------|----------------------------------------------
|  BUFR |             |   0  |  0  |  0 |    2   |    0   |      0 |      0 |   0  |   0  |  0  |   0  | "wr_clk_chd_bufr_div8"
|-------|-------------|------|-----|----|--------|--------|--------|--------|------|------|-----|------|----------------------------------------------


Clock-Region: <CLOCKREGION_X1Y3>
  key resource utilizations (used/available): edge-bufios - 1/2; bufrs - 2/2; regional-clock-spines - 2/2
|-----------------------------------------------------------------------------------------------------------------------------------------------------
|       |    clock    | BRAM |     |    |        |        |        |        |      |      |     |      |
|       |    region   | FIFO | DCM | GT | ILOGIC | OLOGIC | SLICEM | SLICEL | MULT | EMAC | PPC | PCIe | <- (Types of Resources in Clock Region)
|-------|-------------|------|-----|----|--------|--------|--------|--------|------|------|-----|------|----------------------------------------------
|       |CurrentRegion|   8  |  0  |  0 |   32   |   32   |    384 |    384 |   0  |   0  |  0  |   0  | <- Available resources in this current region
|-------|-------------|------|-----|----|--------|--------|--------|--------|------|------|-----|------|----------------------------------------------
|       | Lower Region|   8  |  0  |  0 |   32   |   32   |    384 |    384 |   0  |   0  |  0  |   0  | <- Available resources in the lower region
|-------|-------------|------|-----|----|--------|--------|--------|--------|------|------|-----|------|----------------------------------------------
| clock |    region   |                                                                                -----------------------------------------------
|  type |  expansion  |                                                                                | <IO/Regional clock Net Name>
|-------|-------------|------|-----|----|--------|--------|--------|--------|------|------|-----|------|----------------------------------------------
| BUFIO |             |   0  |  0  |  0 |    2   |    0   |      0 |      0 |   0  |   0  |  0  |   0  | "wr_clk_chb_bufio"
|-------|-------------|------|-----|----|--------|--------|--------|--------|------|------|-----|------|----------------------------------------------
|  BUFR |             |   1  |  0  |  0 |    0   |    0   |      0 |     23 |   0  |   0  |  0  |   0  | "wr_clk_chb_bufr"
|-------|-------------|------|-----|----|--------|--------|--------|--------|------|------|-----|------|----------------------------------------------
|  BUFR |             |   0  |  0  |  0 |    2   |    0   |      0 |      0 |   0  |   0  |  0  |   0  | "wr_clk_chb_bufr_div8"
|-------|-------------|------|-----|----|--------|--------|--------|--------|------|------|-----|------|----------------------------------------------




######################################################################################
# SECONDARY CLOCK NET DISTRIBUTION UCF REPORT:
#
# Number of Secondary Clock Regions : 8
# Number of Secondary Clock Networks: 12
#
# 
######################################################################################

# IO-Clock "wr_clk_chd_bufio" driven by "BUFIO_X0Y7"
INST "wr_clk_chd_core/BUFIO_inst" LOC = "BUFIO_X0Y7" ;
NET "wr_clk_chd_bufio" TNM_NET = "TN_wr_clk_chd_bufio" ;
TIMEGRP "TN_wr_clk_chd_bufio" AREA_GROUP = "CLKAG_wr_clk_chd_bufio" ;
AREA_GROUP "CLKAG_wr_clk_chd_bufio" RANGE = CLOCKREGION_X0Y3;


# IO-Clock "wr_clk_chc_bufio" driven by "BUFIO_X0Y5"
INST "wr_clk_chc_core/BUFIO_inst" LOC = "BUFIO_X0Y5" ;
NET "wr_clk_chc_bufio" TNM_NET = "TN_wr_clk_chc_bufio" ;
TIMEGRP "TN_wr_clk_chc_bufio" AREA_GROUP = "CLKAG_wr_clk_chc_bufio" ;
AREA_GROUP "CLKAG_wr_clk_chc_bufio" RANGE = CLOCKREGION_X0Y2;


# IO-Clock "wr_clk_chb_bufio" driven by "BUFIO_X2Y7"
INST "wr_clk_chb_core/BUFIO_inst" LOC = "BUFIO_X2Y7" ;
NET "wr_clk_chb_bufio" TNM_NET = "TN_wr_clk_chb_bufio" ;
TIMEGRP "TN_wr_clk_chb_bufio" AREA_GROUP = "CLKAG_wr_clk_chb_bufio" ;
AREA_GROUP "CLKAG_wr_clk_chb_bufio" RANGE = CLOCKREGION_X1Y3;


# IO-Clock "wr_clk_cha_bufio" driven by "BUFIO_X2Y4"
INST "wr_clk_cha_core/BUFIO_inst" LOC = "BUFIO_X2Y4" ;
NET "wr_clk_cha_bufio" TNM_NET = "TN_wr_clk_cha_bufio" ;
TIMEGRP "TN_wr_clk_cha_bufio" AREA_GROUP = "CLKAG_wr_clk_cha_bufio" ;
AREA_GROUP "CLKAG_wr_clk_cha_bufio" RANGE = CLOCKREGION_X1Y2;


# Regional-Clock "wr_clk_chd_bufr" driven by "BUFR_X0Y7"
INST "wr_clk_chd_core/BUFR_inst" LOC = "BUFR_X0Y7" ;
NET "wr_clk_chd_bufr" TNM_NET = "TN_wr_clk_chd_bufr" ;
TIMEGRP "TN_wr_clk_chd_bufr" AREA_GROUP = "CLKAG_wr_clk_chd_bufr" ;
AREA_GROUP "CLKAG_wr_clk_chd_bufr" RANGE = CLOCKREGION_X0Y3;


# Regional-Clock "wr_clk_chd_bufr_div8" driven by "BUFR_X0Y6"