correlate_and_accumulate.twr

如何使用ISE和FPGA使用指南

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Release 9.1.01i Trace 
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

Y:\XILI\FISE_9_1i_SP1\bin\nt\trce.exe -ise
R:/training/training/desperf/labs/fpga_editor/fpga_editor_lab.ise -intstyle ise
-e 3 -s 12 -xml correlate_and_accumulate correlate_and_accumulate.ncd -o
correlate_and_accumulate.twr correlate_and_accumulate.pcf -ucf
correlate_and_accumulate.ucf

Design file:              correlate_and_accumulate.ncd
Physical constraint file: correlate_and_accumulate.pcf
Device,package,speed:     xc4vlx15,sf363,-12 (PRODUCTION 1.63 2006-12-13, STEPPING level 1)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock rd_clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  | Clock  |
Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
------------+------------+------------+------------------+--------+
reset       |    5.793(R)|   -1.944(R)|rd_clk_bufg       |   0.000|
------------+------------+------------+------------------+--------+

Setup/Hold to clock wr_clk_cha
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  | Clock  |
Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
------------+------------+------------+------------------+--------+
data_cha    |   -0.350(R)|    0.826(R)|wr_clk_cha_bufio  |   0.000|
reset       |    4.199(R)|   -1.414(R)|wr_clk_cha_bufr   |   0.000|
------------+------------+------------+------------------+--------+

Setup/Hold to clock wr_clk_chb
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  | Clock  |
Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
------------+------------+------------+------------------+--------+
data_chb    |   -0.367(R)|    0.845(R)|wr_clk_chb_bufio  |   0.000|
reset       |    3.888(R)|   -1.562(R)|wr_clk_chb_bufr   |   0.000|
------------+------------+------------+------------------+--------+

Setup/Hold to clock wr_clk_chc
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  | Clock  |
Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
------------+------------+------------+------------------+--------+
data_chc    |   -0.342(R)|    0.825(R)|wr_clk_chc_bufio  |   0.000|
reset       |    2.785(R)|   -0.794(R)|wr_clk_chc_bufr   |   0.000|
------------+------------+------------+------------------+--------+

Setup/Hold to clock wr_clk_chd
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  | Clock  |
Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
------------+------------+------------+------------------+--------+
data_chd    |   -0.364(R)|    0.850(R)|wr_clk_chd_bufio  |   0.000|
reset       |    2.956(R)|   -0.571(R)|wr_clk_chd_bufr   |   0.000|
------------+------------+------------+------------------+--------+

Clock rd_clk to Pad
-------------+------------+------------------+--------+
             | clk (edge) |                  | Clock  |
Destination  |   to PAD   |Internal Clock(s) | Phase  |
-------------+------------+------------------+--------+
final_data[0]|    3.985(R)|rd_clk_bufg       |   0.000|
final_data[1]|    3.860(R)|rd_clk_bufg       |   0.000|
final_data[2]|    4.147(R)|rd_clk_bufg       |   0.000|
final_data[3]|    4.174(R)|rd_clk_bufg       |   0.000|
final_data[4]|    3.839(R)|rd_clk_bufg       |   0.000|
final_data[5]|    3.975(R)|rd_clk_bufg       |   0.000|
final_data[6]|    4.141(R)|rd_clk_bufg       |   0.000|
final_data[7]|    3.963(R)|rd_clk_bufg       |   0.000|
mac_cha[0]   |    3.083(R)|rd_clk_bufg       |   0.000|
mac_cha[1]   |    3.071(R)|rd_clk_bufg       |   0.000|
mac_cha[2]   |    3.064(R)|rd_clk_bufg       |   0.000|
mac_cha[3]   |    3.064(R)|rd_clk_bufg       |   0.000|
mac_cha[4]   |    3.069(R)|rd_clk_bufg       |   0.000|
mac_cha[5]   |    3.068(R)|rd_clk_bufg       |   0.000|
mac_cha[6]   |    3.076(R)|rd_clk_bufg       |   0.000|
mac_cha[7]   |    3.077(R)|rd_clk_bufg       |   0.000|
mac_cha[8]   |    3.066(R)|rd_clk_bufg       |   0.000|
mac_cha[9]   |    3.062(R)|rd_clk_bufg       |   0.000|
mac_cha[10]  |    3.086(R)|rd_clk_bufg       |   0.000|
mac_cha[11]  |    3.088(R)|rd_clk_bufg       |   0.000|
mac_cha[12]  |    3.080(R)|rd_clk_bufg       |   0.000|
mac_cha[13]  |    3.075(R)|rd_clk_bufg       |   0.000|
mac_cha[14]  |    3.112(R)|rd_clk_bufg       |   0.000|
mac_cha[15]  |    3.119(R)|rd_clk_bufg       |   0.000|
mac_cha[16]  |    3.101(R)|rd_clk_bufg       |   0.000|
mac_cha[17]  |    3.098(R)|rd_clk_bufg       |   0.000|
mac_cha[18]  |    3.117(R)|rd_clk_bufg       |   0.000|
mac_cha[19]  |    3.122(R)|rd_clk_bufg       |   0.000|
mac_cha[20]  |    3.099(R)|rd_clk_bufg       |   0.000|
mac_chb[0]   |    3.099(R)|rd_clk_bufg       |   0.000|
mac_chb[1]   |    3.109(R)|rd_clk_bufg       |   0.000|
mac_chb[2]   |    3.117(R)|rd_clk_bufg       |   0.000|
mac_chb[3]   |    3.098(R)|rd_clk_bufg       |   0.000|
mac_chb[4]   |    3.098(R)|rd_clk_bufg       |   0.000|
mac_chb[5]   |    3.115(R)|rd_clk_bufg       |   0.000|
mac_chb[6]   |    3.119(R)|rd_clk_bufg       |   0.000|
mac_chb[7]   |    3.104(R)|rd_clk_bufg       |   0.000|
mac_chb[8]   |    3.102(R)|rd_clk_bufg       |   0.000|
mac_chb[9]   |    3.115(R)|rd_clk_bufg       |   0.000|
mac_chb[10]  |    3.124(R)|rd_clk_bufg       |   0.000|
mac_chb[11]  |    3.099(R)|rd_clk_bufg       |   0.000|
mac_chb[12]  |    3.103(R)|rd_clk_bufg       |   0.000|
mac_chb[13]  |    3.108(R)|rd_clk_bufg       |   0.000|
mac_chb[14]  |    3.117(R)|rd_clk_bufg       |   0.000|
mac_chb[15]  |    3.111(R)|rd_clk_bufg       |   0.000|
mac_chb[16]  |    3.111(R)|rd_clk_bufg       |   0.000|
mac_chb[17]  |    3.117(R)|rd_clk_bufg       |   0.000|
mac_chb[18]  |    3.121(R)|rd_clk_bufg       |   0.000|
mac_chb[19]  |    3.123(R)|rd_clk_bufg       |   0.000|
mac_chb[20]  |    3.116(R)|rd_clk_bufg       |   0.000|
mac_chc[0]   |    3.161(R)|rd_clk_bufg       |   0.000|
mac_chc[1]   |    3.162(R)|rd_clk_bufg       |   0.000|
mac_chc[2]   |    3.170(R)|rd_clk_bufg       |   0.000|
mac_chc[3]   |    3.178(R)|rd_clk_bufg       |   0.000|
mac_chc[4]   |    3.164(R)|rd_clk_bufg       |   0.000|
mac_chc[5]   |    3.164(R)|rd_clk_bufg       |   0.000|
mac_chc[6]   |    3.170(R)|rd_clk_bufg       |   0.000|
mac_chc[7]   |    3.170(R)|rd_clk_bufg       |   0.000|
mac_chc[8]   |    3.157(R)|rd_clk_bufg       |   0.000|
mac_chc[9]   |    3.156(R)|rd_clk_bufg       |   0.000|
mac_chc[10]  |    3.181(R)|rd_clk_bufg       |   0.000|
mac_chc[11]  |    3.184(R)|rd_clk_bufg       |   0.000|
mac_chc[12]  |    3.177(R)|rd_clk_bufg       |   0.000|
mac_chc[13]  |    3.173(R)|rd_clk_bufg       |   0.000|
mac_chc[14]  |    3.210(R)|rd_clk_bufg       |   0.000|
mac_chc[15]  |    3.218(R)|rd_clk_bufg       |   0.000|
mac_chc[16]  |    3.200(R)|rd_clk_bufg       |   0.000|
mac_chc[17]  |    3.203(R)|rd_clk_bufg       |   0.000|
mac_chc[18]  |    3.216(R)|rd_clk_bufg       |   0.000|
mac_chc[19]  |    3.222(R)|rd_clk_bufg       |   0.000|
mac_chc[20]  |    3.199(R)|rd_clk_bufg       |   0.000|
mac_chd[0]   |    3.199(R)|rd_clk_bufg       |   0.000|
mac_chd[1]   |    3.209(R)|rd_clk_bufg       |   0.000|
mac_chd[2]   |    3.217(R)|rd_clk_bufg       |   0.000|
mac_chd[3]   |    3.197(R)|rd_clk_bufg       |   0.000|
mac_chd[4]   |    3.196(R)|rd_clk_bufg       |   0.000|
mac_chd[5]   |    3.214(R)|rd_clk_bufg       |   0.000|
mac_chd[6]   |    3.215(R)|rd_clk_bufg       |   0.000|
mac_chd[7]   |    3.218(R)|rd_clk_bufg       |   0.000|
mac_chd[8]   |    3.211(R)|rd_clk_bufg       |   0.000|
mac_chd[9]   |    3.206(R)|rd_clk_bufg       |   0.000|
mac_chd[10]  |    3.215(R)|rd_clk_bufg       |   0.000|
mac_chd[11]  |    3.223(R)|rd_clk_bufg       |   0.000|
mac_chd[12]  |    3.198(R)|rd_clk_bufg       |   0.000|
mac_chd[13]  |    3.204(R)|rd_clk_bufg       |   0.000|
mac_chd[14]  |    3.209(R)|rd_clk_bufg       |   0.000|
mac_chd[15]  |    3.218(R)|rd_clk_bufg       |   0.000|
mac_chd[16]  |    3.214(R)|rd_clk_bufg       |   0.000|
mac_chd[17]  |    3.210(R)|rd_clk_bufg       |   0.000|
mac_chd[18]  |    3.219(R)|rd_clk_bufg       |   0.000|
mac_chd[19]  |    3.224(R)|rd_clk_bufg       |   0.000|
mac_chd[20]  |    3.226(R)|rd_clk_bufg       |   0.000|
mac_dv[0]    |    4.970(R)|rd_clk_bufg       |   0.000|
mac_dv[1]    |    6.441(R)|rd_clk_bufg       |   0.000|
mac_dv[2]    |    4.773(R)|rd_clk_bufg       |   0.000|
mac_dv[3]    |    4.817(R)|rd_clk_bufg       |   0.000|
valid_ch[0]  |    5.118(R)|rd_clk_bufg       |   0.000|
valid_ch[1]  |    5.171(R)|rd_clk_bufg       |   0.000|
valid_ch[2]  |    4.836(R)|rd_clk_bufg       |   0.000|
valid_ch[3]  |    4.932(R)|rd_clk_bufg       |   0.000|
-------------+------------+------------------+--------+

Clock to Setup on destination clock rd_clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
rd_clk         |    3.694|         |         |         |
wr_clk_cha     |    2.304|         |         |         |
wr_clk_chb     |    2.171|         |         |         |
wr_clk_chc     |    2.381|         |         |         |
wr_clk_chd     |    2.417|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock wr_clk_cha
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
wr_clk_cha     |    3.476|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock wr_clk_chb
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
wr_clk_chb     |    3.114|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock wr_clk_chc
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
wr_clk_chc     |    3.174|         |         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock wr_clk_chd
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
wr_clk_chd     |    3.217|         |         |         |
---------------+---------+---------+---------+---------+


Analysis completed Fri Apr 06 14:07:07 2007 
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Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 216 MB