correlate_and_accumulate_map.map

如何使用ISE和FPGA使用指南

Release 9.1.01i Map J.31
Xilinx Map Application Log File for Design 'correlate_and_accumulate'

Design Information
------------------
Command Line   : Y:\XILI\FISE_9_1i_SP1\bin\nt\map.exe -ise
R:/training/training/desperf/labs/fpga_editor/fpga_editor_lab.ise -intstyle ise
-p xc4vlx15-sf363-12 -cm area -pr b -k 4 -c 100 -o
correlate_and_accumulate_map.ncd correlate_and_accumulate.ngd
correlate_and_accumulate.pcf 
Target Device  : xc4vlx15
Target Package : sf363
Target Speed   : -12
Mapper Version : virtex4 -- $Revision: 1.36 $
Mapped Date    : Fri Apr 06 14:05:35 2007

Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:    5
Logic Utilization:
  Number of Slice Flip Flops:         267 out of  12,288    2%
  Number of 4 input LUTs:             603 out of  12,288    4%
Logic Distribution:
  Number of occupied Slices:                          403 out of   6,144    6%
    Number of Slices containing only related logic:     403 out of     403  100%
    Number of Slices containing unrelated logic:          0 out of     403    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:         603 out of  12,288    4%
  Number of bonded IOBs:              110 out of     240   45%
  Number of BUFG/BUFGCTRLs:             1 out of      32    3%
    Number used as BUFGs:                1
    Number used as BUFGCTRLs:            0
  Number of FIFO16/RAMB16s:             4 out of      48    8%
    Number used as FIFO16s:              4
    Number used as RAMB16s:              0
  Number of DSP48s:                     4 out of      32   12%
  Number of DCM_ADVs:                   1 out of       4   25%
  Number of BUFRs:                      8 out of      16   50%
  Number of ISERDESs:                   8 out of     320    2%
  Number of BUFIOs:                     4 out of      24   16%

Total equivalent gate count for design:  268,594
Additional JTAG gate count for IOBs:  5,280
Peak Memory Usage:  205 MB
Total REAL time to MAP completion:  16 secs 
Total CPU time to MAP completion:   15 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "correlate_and_accumulate_map.mrp" for details.