pn_correlation_xst.vhd

如何使用ISE和FPGA使用指南

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.correlate_and_accumulate_pack.all;
Library UNISIM;
use UNISIM.vcomponents.all;

entity pn_correlation is
    generic (
        K         :     std_logic_vector (7 downto 0) := "10001101");
    port (
        clk_bufio     : in  std_logic;
        clk_bufr_div8 : in  std_logic;
        clk_bufr      : in  std_logic;
        reset         : in  std_logic;
        pn_acq        : in  std_logic;
        data_ch       : in  std_logic;
        pn_fnd        : out std_logic;
        wr_data       : out std_logic_vector (7 downto 0));

end pn_correlation;

architecture rtl of pn_correlation is
    signal sr_data : std_logic_vector(7 downto 0);
    signal gnd, vcc : std_logic;
    signal shift1, shift2 : std_logic;
    
begin  -- rtl

    gnd <= '0';
    vcc <= '1';
    
    wr_data <= sr_data;

      iserdes_master : ISERDES
   -- The following generics specify the behavior of the ISERDES
   generic map (
      BITSLIP_ENABLE => FALSE, -- TRUE/FALSE to enable bitslip controller
      DATA_RATE => "SDR", -- Specify data rate of "DDR" or "SDR" 
      DATA_WIDTH => 8, -- Specify data width - For DDR 4,6,8, or 10 
                       -- For SDR 2,3,4,5,6,7, or 8 
      INIT_Q1 => '0',  -- INIT for Q1 register - '1' or '0' 
      INIT_Q2 => '0',  -- INIT for Q2 register - '1' or '0' 
      INIT_Q3 => '0',  -- INIT for Q3 register - '1' or '0' 
      INIT_Q4 => '0',  -- INIT for Q4 register - '1' or '0' 
      INTERFACE_TYPE => "NETWORKING", -- Use model - "MEMORY" or "NETWORKING" 
      IOBDELAY => "NONE", -- Specify outputs where delay chain will be applied
                          -- "NONE", "IBUF", "IFD", or "BOTH" 
      IOBDELAY_TYPE => "DEFAULT", -- Set tap delay "DEFAULT", "FIXED", or "VARIABLE" 
      IOBDELAY_VALUE => 0, -- Set initial tap delay to an integer from 0 to 63
      NUM_CE => 2, -- Define number or clock enables to an integer of 1 or 2
      SERDES_MODE => "MASTER", --Set SERDES mode to "MASTER" or "SLAVE" 
      SRVAL_Q1 => '0', -- Define Q1 output value upon SR assertion - '1' or '0' 
      SRVAL_Q2 => '0', -- Define Q1 output value upon SR assertion - '1' or '0' 
      SRVAL_Q3 => '0', -- Define Q1 output value upon SR assertion - '1' or '0' 
      SRVAL_Q4 => '0') -- Define Q1 output value upon SR assertion - '1' or '0' 
   port map (
      O => open,    -- 1-bit output
      Q1 => sr_data(0),  -- 1-bit output
      Q2 => sr_data(1),  -- 1-bit output
      Q3 => sr_data(2),  -- 1-bit output
      Q4 => sr_data(3),  -- 1-bit output
      Q5 => sr_data(4),  -- 1-bit output
      Q6 => sr_data(5),  -- 1-bit output
      SHIFTOUT1 => shift1, -- 1-bit output
      SHIFTOUT2 => shift2, -- 1-bit output
      BITSLIP => gnd,     -- 1-bit input
      CE1 => vcc,        -- 1-bit input
      CE2 => vcc,        -- 1-bit input
      CLK => clk_bufio,        -- 1-bit input
      CLKDIV => clk_bufr_div8,  -- 1-bit input
      D => data_ch,            -- 1-bit input
      DLYCE => gnd,    -- 1-bit input
      DLYINC => gnd,  -- 1-bit input
      DLYRST => gnd,  -- 1-bit input
      OCLK => gnd,      -- 1-bit input
      REV => gnd,        -- 1-bit input
      SHIFTIN1 => gnd, -- 1-bit input
      SHIFTIN2 => gnd, -- 1-bit input
      SR => reset            -- 1-bit input
   );    
      iserdes_slave : ISERDES
   -- The following generics specify the behavior of the ISERDES
   generic map (
      BITSLIP_ENABLE => FALSE , -- TRUE/FALSE to enable bitslip controller
      DATA_RATE => "SDR" , -- Specify data rate of "DDR" or "SDR" 
      DATA_WIDTH => 8 , -- Specify data width - For DDR 4,6,8, or 10 
                       -- For SDR 2,3,4,5,6,7, or 8 
      INIT_Q1 => '0',  -- INIT for Q1 register - '1' or '0' 
      INIT_Q2 => '0',  -- INIT for Q2 register - '1' or '0' 
      INIT_Q3 => '0',  -- INIT for Q3 register - '1' or '0' 
      INIT_Q4 => '0',  -- INIT for Q4 register - '1' or '0' 
      INTERFACE_TYPE => "NETWORKING", -- Use model - "MEMORY" or "NETWORKING" 
      IOBDELAY => "NONE", -- Specify outputs where delay chain will be applied
                          -- "NONE", "IBUF", "IFD", or "BOTH" 
      IOBDELAY_TYPE => "DEFAULT", -- Set tap delay "DEFAULT", "FIXED", or "VARIABLE" 
      IOBDELAY_VALUE => 0, -- Set initial tap delay to an integer from 0 to 63
      NUM_CE => 2, -- Define number or clock enables to an integer of 1 or 2
      SERDES_MODE => "SLAVE" , --Set SERDES mode to "MASTER" or "SLAVE" 
      SRVAL_Q1 => '0', -- Define Q1 output value upon SR assertion - '1' or '0' 
      SRVAL_Q2 => '0', -- Define Q1 output value upon SR assertion - '1' or '0' 
      SRVAL_Q3 => '0', -- Define Q1 output value upon SR assertion - '1' or '0' 
      SRVAL_Q4 => '0') -- Define Q1 output value upon SR assertion - '1' or '0' 
   port map (
      O => open,    -- 1-bit output
      Q1 => open,  -- 1-bit output
      Q2 => open,  -- 1-bit output
      Q3 => sr_data(6) ,  -- 1-bit output
      Q4 => sr_data(7) ,  -- 1-bit output
      Q5 => open,  -- 1-bit output
      Q6 => open,  -- 1-bit output
      SHIFTOUT1 => open, -- 1-bit output
      SHIFTOUT2 => open, -- 1-bit output
      BITSLIP => gnd ,     -- 1-bit input
      CE1 => vcc,        -- 1-bit input
      CE2 => vcc,        -- 1-bit input
      CLK => clk_bufio ,        -- 1-bit input
      CLKDIV => clk_bufr_div8 ,  -- 1-bit input
      D => gnd,            -- 1-bit input
      DLYCE => gnd,    -- 1-bit input
      DLYINC => gnd,  -- 1-bit input
      DLYRST => gnd,  -- 1-bit input
      OCLK => gnd,      -- 1-bit input
      REV => gnd,        -- 1-bit input
      SHIFTIN1 => shift1 , -- 1-bit input
      SHIFTIN2 => shift2 , -- 1-bit input
      SR => reset            -- 1-bit input
   );
    
    -- pn_rake
    pn_rake: process (clk_bufr)
        variable result : std_logic_vector (7 downto 0);
        variable agree, disagree, correlation : integer;
    begin  -- process pn_rake
        if rising_edge(clk_bufr) then
            if reset = '1' then             
                pn_fnd <= '0';
            else
                -- default
                pn_fnd <= '0';
                if pn_acq = '1' then
                    for j in 0 to 7 loop
                        if K(j) = '1' then
                            result(j) := K(j) and sr_data(j);
                        else
                            result(j) := not K(j) and not sr_data(j);
                        end if;
                    end loop;  -- j
                    -- 
                    agree := 0;
                    disagree := 0;

                    for i in 0 to 7 loop
                        case result(i) is
                            when '0' =>
                                disagree := disagree + 1;
                            when '1' =>
                                agree := agree + 1;
                            when others => null;
                        end case;
                    end loop;  -- i
                    correlation := agree - disagree;

                    if correlation = 8 then
                        pn_fnd <= '1';
                    else
                        pn_fnd <= '0';
                    end if;
                end if;
            end if;
        end if;
    end process pn_rake;

end rtl;