ch_fifo.vhd

如何使用ISE和FPGA使用指南

library ieee;
use ieee.std_logic_1164.all;
library UNISIM;
use UNISIM.vcomponents.all;

entity ch_fifo is
    generic (
        K              :     std_logic_vector (7 downto 0) := "10001101");
    port (
        rd_clk         : in  std_logic;
        clk_bufio      : in  std_logic;
        clk_bufr       : in  std_logic;
        clk_bufr_div8  : in  std_logic;
        reset          : in  std_logic;
        data_ch        : in  std_logic;
        rd             : in  std_logic;
        pn_lock_rd_clk : out std_logic;
        almost_full    : out std_logic;
        almost_empty   : out std_logic;
        full           : out std_logic;
        empty          : out std_logic;
        rd_data        : out std_logic_vector (7 downto 0));
end ch_fifo;

architecture structure of ch_fifo is

    component pn_correlator
        generic (
            K             :     std_logic_vector (7 downto 0) := "10001101");
        port (
            clk_bufr      : in  std_logic;
            clk_bufio     : in  std_logic;
            clk_bufr_div8 : in  std_logic;
            reset         : in  std_logic;
            data_ch       : in  std_logic;
            wr            : out std_logic;
            pn_lock       : out std_logic;
            wr_addr_srst  : out std_logic;
            wr_data       : out std_logic_vector(7 downto 0));
    end component pn_correlator;

    component pn_lock_wr2rd
        port (
            rd_clk         : in  std_logic;
            reset          : in  std_logic;
            pn_lock        : in  std_logic;
            pn_lock_rd_clk : out std_logic);
    end component pn_lock_wr2rd;

    component flags_wr2rd
        port (
            rd_clk            : in  std_logic;
            reset             : in  std_logic;
            fifo_full         : in  std_logic;
            fifo_almost_full  : in  std_logic;
            fifo_empty        : in  std_logic;
            fifo_almost_empty : in  std_logic;
            full              : out std_logic;  -- Is on the wr_clk domain
            almost_full       : out std_logic;  -- Is on the wr_clk domain
            empty             : out std_logic;
            almost_empty      : out std_logic);
    end component flags_wr2rd;

    signal pn_lock, wr, wr_addr_srst : std_logic;
    signal rd_err, wr_err            : std_logic;
    signal rd_addr, wr_addr          : std_logic_vector (11 downto 0);
    signal wr_data                   : std_logic_vector (7 downto 0);
    signal gnd                       : std_logic;
    signal fifo_full, fifo_almost_full, fifo_empty, fifo_almost_empty : std_logic;
begin  -- structure

    gnd <= '0';

    pn_correlator_inst : pn_correlator
        generic map (
            K             => K)
        port map (
            clk_bufio     => clk_bufio,
            clk_bufr      => clk_bufr,
            clk_bufr_div8 => clk_bufr_div8,
            reset         => reset,
            data_ch       => data_ch,
            wr            => wr,
            pn_lock       => pn_lock,
            wr_addr_srst  => wr_addr_srst,
            wr_data       => wr_data);

    pn_lock_wr2rd_inst : pn_lock_wr2rd
        port map(
            rd_clk         => rd_clk,
            reset          => reset,
            pn_lock        => pn_lock,
            pn_lock_rd_clk => pn_lock_rd_clk);

    flags_wr2rd_inst : flags_wr2rd
        port map(
            rd_clk            => rd_clk,
            reset             => reset,
            fifo_full         => fifo_full,
            fifo_almost_full  => fifo_almost_full,
            fifo_empty        => fifo_empty,
            fifo_almost_empty => fifo_almost_empty,
            full              => full,
            almost_full       => almost_full,
            empty             => empty,
            almost_empty      => almost_empty);

    fifo16_inst : fifo16
        generic map (
            ALMOST_FULL_OFFSET      => X"008",  -- Sets almost full threshold
            ALMOST_EMPTY_OFFSET     => X"008",  -- Sets the almost empty threshold
            DATA_WIDTH              => 9,  -- Sets data width to 4, 9, 18, or 36
            FIRST_WORD_FALL_THROUGH => true)  --Sets the FIFO FWFT to TRUE or FALSE
        port map (
            ALMOSTEMPTY             => fifo_almost_empty,  -- 1-bit almost empty output flag
            ALMOSTFULL              => fifo_almost_full,  -- 1-bit almost full output flag
            DO (31 downto 8)        => open,  -- Unused data output
            DO (7 downto 0)         => rd_data,  -- 8-bit data output
            DOP (3 downto 1)        => open,  -- Unused parity data output
            DOP (0)                 => open,  -- 1-bit parity data output
            EMPTY                   => fifo_empty,  -- 1-bit empty output flag
            FULL                    => fifo_full,  -- 1-bit full output flag
            RDCOUNT                 => rd_addr,  -- 12-bit read count output
            RDERR                   => rd_err,  -- 1-bit read error output
            WRCOUNT                 => wr_addr,  -- 12-bit write count output
            WRERR                   => wr_err,  -- 1-bit write error
            DI (31 downto 8)        => X"000000",  -- Unused data inputs tied to ground
            DI (7 downto 0)         => wr_data,  -- 8-bit data input
            DIP (3 downto 1)        => "000",  -- Unused parity inputs tied to ground
            DIP (0)                 => gnd,  -- 1-bit partity input
            RDCLK                   => rd_clk,  -- 1-bit read clock input
            RDEN                    => rd,  -- 1-bit read enable input
            RST                     => reset,  -- 1-bit reset input
            WRCLK                   => clk_bufr,  -- 1-bit write clock input
            WREN                    => wr);  -- 1-bit write enable input

end structure;