flags_wr2rd.vhd

如何使用ISE和FPGA使用指南

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity flags_wr2rd is
    port (
        rd_clk            : in  std_logic;
        reset             : in  std_logic;
        fifo_full         : in  std_logic;
        fifo_almost_full  : in  std_logic;
        fifo_empty        : in  std_logic;
        fifo_almost_empty : in  std_logic;
        full              : out std_logic;  -- Is on the wr_clk domain
        almost_full       : out std_logic;  -- Is on the wr_clk domain
        empty             : out std_logic;
        almost_empty      : out std_logic);
end flags_wr2rd;

architecture rtl of flags_wr2rd is
    signal full_p0, almost_full_p0, empty_p0, almost_empty_p0 : std_logic;
begin  -- rtl

    --_____________________________________________________________________________________
    -- Cross clock domains for full & almost_full from wr_clk to rd_clk
    --_____________________________________________________________________________________
    process (rd_clk)
    begin  -- process
        if rising_edge(rd_clk) then                    -- rising clock edge
            if reset = '1' then
                full_p0         <= '0';
                almost_full_p0  <= '0';
                empty_p0        <= '0';
                almost_empty_p0 <= '0';
                full            <= '0';
                almost_full     <= '0';
                empty           <= '0';
                almost_empty    <= '0';
            else
                full_p0         <= fifo_full;          -- Metastable reg
                almost_full_p0  <= fifo_almost_full;   -- Metastable reg
                empty_p0        <= fifo_empty;         -- balance reg
                almost_empty_p0 <= fifo_almost_empty;  -- balance reg
                full            <= full_p0;            -- cross reg
                almost_full     <= almost_full_p0;     -- cross reg
                empty           <= empty_p0;           -- balance reg
                almost_empty    <= almost_empty_p0;    -- balance reg
--                 full <= fifo_full;
--                 almost_full <= fifo_almost_full;
--                 empty <= fifo_empty;
--                 almost_empty <= fifo_almost_empty;
            end if;
        end if;
    end process;
end architecture rtl;