correlate_and_accumulate_xst.vhd

如何使用ISE和FPGA使用指南

library ieee;
use ieee.std_logic_1164.all;
Library UNISIM;
use UNISIM.vcomponents.all;

entity correlate_and_accumulate is
    generic (
        Ka         :     std_logic_vector (7 downto 0) := "10001101";
        Kb         :     std_logic_vector (7 downto 0) := "11100101";
        Kc         :     std_logic_vector (7 downto 0) := "00101110";
        Kd         :     std_logic_vector (7 downto 0) := "11010001");
    port (
        rd_clk     : in  std_logic;
        wr_clk_cha : in  std_logic;
        wr_clk_chb : in  std_logic;
        wr_clk_chc : in  std_logic;
        reset      : in  std_logic;
        wr_clk_chd : in  std_logic;
        data_cha   : in  std_logic;
        data_chb   : in  std_logic;
        data_chc   : in  std_logic;
        data_chd   : in  std_logic;
        final_data : out std_logic_vector(7 downto 0);
        mac_cha    : out std_logic_vector (20 downto 0);
        mac_chb    : out std_logic_vector (20 downto 0);
        mac_chc    : out std_logic_vector (20 downto 0);
        mac_chd    : out std_logic_vector (20 downto 0);
        mac_dv     : out std_logic_vector (3 downto 0);
        valid_ch   : out std_logic_vector (3 downto 0));
end correlate_and_accumulate;

architecture structure of correlate_and_accumulate is

    component data_control
        port (
            clk            : in  std_logic;
            reset          : in  std_logic;
            rd_data_cha    : in  std_logic_vector (7 downto 0);
            rd_data_chb    : in  std_logic_vector (7 downto 0);
            rd_data_chc    : in  std_logic_vector (7 downto 0);
            rd_data_chd    : in  std_logic_vector (7 downto 0);
            pn_lock_rd_clk : in  std_logic_vector(3 downto 0);
            almost_full    : in  std_logic_vector(3 downto 0);
            almost_empty   : in  std_logic_vector(3 downto 0);
            full           : in  std_logic_vector(3 downto 0);
            empty          : in  std_logic_vector(3 downto 0);
            rd             : out std_logic_vector (3 downto 0);
            valid_ch       : out std_logic_vector (3 downto 0);
            mac_dv         : out std_logic_vector (3 downto 0);
            final_data     : out std_logic_vector (7 downto 0);
            mac_cha        : out std_logic_vector (20 downto 0);
            mac_chb        : out std_logic_vector (20 downto 0);
            mac_chc        : out std_logic_vector (20 downto 0);
            mac_chd        : out std_logic_vector (20 downto 0));
    end component data_control;

    component ch_fifo
        generic (
            K              :     std_logic_vector (7 downto 0) := "10001101");
        port (
            rd_clk         : in  std_logic;
            clk_bufio      : in  std_logic;
            clk_bufr       : in  std_logic;
            clk_bufr_div8  : in  std_logic;
            reset          : in  std_logic;
            data_ch        : in  std_logic;
            rd             : in  std_logic;
            pn_lock_rd_clk : out std_logic;
            almost_full    : out std_logic;
            almost_empty   : out std_logic;
            full           : out std_logic;
            empty          : out std_logic;
            rd_data        : out std_logic_vector (7 downto 0));
    end component ch_fifo;
	 
	component wr_clk_core 
    port ( wr_clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           wr_clk_bufio : out  STD_LOGIC;
           wr_clk_bufr : out  STD_LOGIC;
           wr_clk_bufr_div8 : out  STD_LOGIC);
	end component wr_clk_core;
	
    signal rd_data_cha, rd_data_chb, rd_data_chc, rd_data_chd                                     : std_logic_vector (7 downto 0);
    signal rd, pn_lock_rd_clk, almost_full, almost_empty, full, empty                             : std_logic_vector (3 downto 0);
    signal rd_clk_bufg                                                                             : std_logic;
    signal wr_clk_cha_bufio, wr_clk_chb_bufio, wr_clk_chc_bufio, wr_clk_chd_bufio                 : std_logic;
    signal wr_clk_cha_bufr, wr_clk_chb_bufr, wr_clk_chc_bufr, wr_clk_chd_bufr                     : std_logic;
    signal wr_clk_cha_bufr_div8, wr_clk_chb_bufr_div8, wr_clk_chc_bufr_div8, wr_clk_chd_bufr_div8 : std_logic;

    signal vcc, gnd : std_logic;
begin  -- structure

    vcc <= '1';
    gnd <= '0';



    data_control_inst : data_control
        port map(
            clk            => rd_clk_bufg,
            reset          => reset,
            rd_data_cha    => rd_data_cha,
            rd_data_chb    => rd_data_chb,
            rd_data_chc    => rd_data_chc,
            rd_data_chd    => rd_data_chd,
            pn_lock_rd_clk => pn_lock_rd_clk,
            almost_full    => almost_full,
            almost_empty   => almost_empty,
            full           => full,
            empty          => empty,
            rd             => rd,
            valid_ch       => valid_ch,
            mac_dv         => mac_dv,
            final_data     => final_data,
            mac_cha        => mac_cha,
            mac_chb        => mac_chb,
            mac_chc        => mac_chc,
            mac_chd        => mac_chd);

    cha_fifo_inst : ch_fifo
        generic map (
            K              => Ka)
        port map(
            rd_clk         => rd_clk_bufg,
            clk_bufio      => wr_clk_cha_bufio,
            clk_bufr       => wr_clk_cha_bufr,
            clk_bufr_div8  => wr_clk_cha_bufr_div8,
            reset          => reset,
            data_ch        => data_cha,
            rd             => rd(0),
            pn_lock_rd_clk => pn_lock_rd_clk(0),
            almost_full    => almost_full(0),
            almost_empty   => almost_empty(0),
            full           => full(0),
            empty          => empty(0),
            rd_data        => rd_data_cha);

    chb_fifo_inst : ch_fifo
        generic map (
            K              => Kb)
        port map(
            rd_clk         => rd_clk_bufg,
            clk_bufio      => wr_clk_chb_bufio,
            clk_bufr       => wr_clk_chb_bufr,
            clk_bufr_div8  => wr_clk_chb_bufr_div8,
            reset          => reset,
            data_ch        => data_chb,
            rd             => rd(1),
            pn_lock_rd_clk => pn_lock_rd_clk(1),
            almost_full    => almost_full(1),
            almost_empty   => almost_empty(1),
            full           => full(1),
            empty          => empty(1),
            rd_data        => rd_data_chb);

    chc_fifo_inst : ch_fifo
        generic map (
            K              => Kc)
        port map(
            rd_clk         => rd_clk_bufg,
            clk_bufio      => wr_clk_chc_bufio,
            clk_bufr       => wr_clk_chc_bufr,
            clk_bufr_div8  => wr_clk_chc_bufr_div8,
            reset          => reset,
            data_ch        => data_chc,
            rd             => rd(2),
            pn_lock_rd_clk => pn_lock_rd_clk(2),
            almost_full    => almost_full(2),
            almost_empty   => almost_empty(2),
            full           => full(2),
            empty          => empty(2),
            rd_data        => rd_data_chc);

    chd_fifo_inst : ch_fifo
        generic map (
            K              => Kd)
        port map(
            rd_clk         => rd_clk_bufg,
            clk_bufio      => wr_clk_chd_bufio,
            clk_bufr       => wr_clk_chd_bufr,
            clk_bufr_div8  => wr_clk_chd_bufr_div8,
            reset          => reset,
            data_ch        => data_chd,
            rd             => rd(3),
            pn_lock_rd_clk => pn_lock_rd_clk(3),
            almost_full    => almost_full(3),
            almost_empty   => almost_empty(3),
            full           => full(3),
            empty          => empty(3),
            rd_data        => rd_data_chd);
				
	wr_clk_cha_core : wr_clk_core
    port map (
		wr_clk 			  => wr_clk_cha,
      reset  			  => reset, 
      wr_clk_bufio 	  => wr_clk_cha_bufio,
      wr_clk_bufr  	  => wr_clk_cha_bufr,
      wr_clk_bufr_div8 => wr_clk_cha_bufr_div8);

	wr_clk_chb_core: wr_clk_core 
    port map (
		wr_clk 			  => wr_clk_chb,
      reset  			  => reset, 
      wr_clk_bufio 	  => wr_clk_chb_bufio,
      wr_clk_bufr  	  => wr_clk_chb_bufr,
      wr_clk_bufr_div8 => wr_clk_chb_bufr_div8);
		
	wr_clk_chc_core: wr_clk_core 
    port map (
		wr_clk 			  => wr_clk_chc,
      reset  			  => reset, 
      wr_clk_bufio 	  => wr_clk_chc_bufio,
      wr_clk_bufr  	  => wr_clk_chc_bufr,
      wr_clk_bufr_div8 => wr_clk_chc_bufr_div8);
		
	wr_clk_chd_core: wr_clk_core
    port map (
		wr_clk 			  => wr_clk_chd,
      reset  			  => reset, 
      wr_clk_bufio 	  => wr_clk_chd_bufio,
      wr_clk_bufr  	  => wr_clk_chd_bufr,
      wr_clk_bufr_div8 => wr_clk_chd_bufr_div8);

end structure;