pn_lock_wr2rd.vhd

如何使用ISE和FPGA使用指南

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity pn_lock_wr2rd is
    port (
        rd_clk         : in  std_logic;
        reset          : in  std_logic;
        pn_lock        : in  std_logic;
        pn_lock_rd_clk : out std_logic);
end pn_lock_wr2rd;

architecture rtl of pn_lock_wr2rd is
    signal pn_lock_rd_clk_p0, pn_lock_rd_clk_i : std_logic;
begin  -- rtl

    --_____________________________________________________________________________________
    -- Cross clock domains for pn_lock from wr_clk to rd_clk
    --_____________________________________________________________________________________
    pn_lock_rd_clk                <= pn_lock_rd_clk_i;
    process (rd_clk)
    begin  -- process
        if rising_edge(rd_clk) then            -- rising clock edge
            if reset = '1' then
                pn_lock_rd_clk_p0 <= '0';
                pn_lock_rd_clk_i  <= '0';
            else
                pn_lock_rd_clk_p0 <= pn_lock;  -- gaurds agains metastability
                pn_lock_rd_clk_i  <= pn_lock_rd_clk_p0;
            end if;
        end if;
    end process;
end architecture rtl;