pn_correlator.vhd

如何使用ISE和FPGA使用指南

library ieee;
use ieee.std_logic_1164.all;

entity pn_correlator is
    generic (
        K : std_logic_vector (7 downto 0) := "10001101");
    port (
        clk_bufio     : in  std_logic;
        clk_bufr      : in  std_logic;
        clk_bufr_div8 : in  std_logic;
        reset         : in  std_logic;
        data_ch       : in  std_logic;
        wr            : out std_logic;
        pn_lock       : out std_logic;
        wr_addr_srst  : out std_logic;
        wr_data       : out std_logic_vector(7 downto 0));

end pn_correlator;

architecture structure of pn_correlator is
	component pn_correlation 
    generic (
        K         :     std_logic_vector (7 downto 0) := "10001101");
    port (
        clk_bufio     : in  std_logic;
        clk_bufr_div8 : in  std_logic;
        clk_bufr      : in  std_logic;
        reset         : in  std_logic;
        pn_acq        : in  std_logic;
        data_ch       : in  std_logic;
        pn_fnd        : out std_logic;
        wr_data       : out std_logic_vector (7 downto 0));

	end component pn_correlation;

    component pn_correlation_fsm 
    port (
        clk_bufr     : in  std_logic;
        reset        : in  std_logic;
        pn_fnd       : in  std_logic;
        wr_addr_srst : out std_logic;
        pn_lock      : out std_logic;
        pn_acq       : out std_logic;
        wr           : out std_logic);
    end component pn_correlation_fsm;
    
    signal pn_fnd, pn_acq : std_logic;
    
begin  -- structure
    
    pn_correlation_inst: pn_correlation
        generic map (
            K => K)
        port map(
            clk_bufio     => clk_bufio,
            clk_bufr      => clk_bufr,
            clk_bufr_div8 => clk_bufr_div8,
            reset         => reset,
            pn_acq        => pn_acq,
            data_ch       => data_ch,
            pn_fnd        => pn_fnd,
            wr_data       => wr_data);

    pn_correlation_fsm_inst : pn_correlation_fsm
        port map(
            clk_bufr     => clk_bufr,
            reset        => reset,
            pn_fnd       => pn_fnd,
            wr_addr_srst => wr_addr_srst,
            pn_lock      => pn_lock,
            pn_acq       => pn_acq,
            wr           => wr);

end structure;