xst.xmsgs

如何使用ISE和FPGA使用指南

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">rd_addr</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">wr_addr_srst</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">wr_addr</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">rd_err</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">wr_err</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">rd_addr</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">wr_addr_srst</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">wr_addr</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">rd_err</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">wr_err</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">rd_addr</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">wr_addr_srst</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">wr_addr</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">rd_err</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">vcc</arg>&gt; is assigned but never used.
</msg>

<msg type="warning" file="Xst" num="646" delta="unknown" >Signal &lt;<arg fmt="%s" index="1">gnd</arg>&gt; is assigned but never used.
</msg>

<msg type="info" file="Xst" num="1767" delta="unknown" >HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">almost_full</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">almost_empty</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">full</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">empty</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">pn_lock_rd_clk</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">almost_full</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">almost_empty</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">full</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">empty</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

<msg type="info" file="Xst" num="2387" delta="unknown" >HDL ADVISOR - A <arg fmt="%d" index="1">2</arg>-bit shift register was found for signal &lt;<arg fmt="%s" index="2">pn_lock_rd_clk</arg>&gt; and currently occupies <arg fmt="%d" index="3">2</arg> logic cells (<arg fmt="%d" index="4">1</arg> slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
</msg>

</messages>