ch_fifo.v

如何使用ISE和FPGA使用指南

module ch_fifo(input rd_clk, 
	       input clk_bufio,
	       input clk_bufr,
	       input clk_bufr_div8,
	       input reset, 
	       input data_ch,
	       input rd,
	       output [7:0] rd_data, 
	       output pn_lock_rd_clk, 
	       output almost_full, 
	       output almost_empty, 
	       output full, 
	       output empty);

    wire 	 pn_lock, wr, wr_addr_srst;
    wire [10:0]  rd_addr, wr_addr;
    wire [7:0] 	 wr_data;
    wire [31:0]  unconnected;
    wire 	 rd_err, wr_err;
    wire 	 fifo_full, fifo_almost_full, fifo_empty, fifo_almost_empty;

    pn_correlator pn_correlator_inst
      (.clk_bufio(clk_bufio),
       .clk_bufr(clk_bufr),
       .clk_bufr_div8(clk_bufr_div8), 
       .reset(reset), 
       .data_ch(data_ch), 
       .wr_data(wr_data), 
       .wr(wr), 
       .pn_lock(pn_lock), 
       .wr_addr_srst(wr_addr_srst));   

    pn_lock_wr2rd pn_lock_wr2rd_inst
      (.rd_clk(rd_clk),
       .reset(reset),
       .pn_lock(pn_lock),
       .pn_lock_rd_clk(pn_lock_rd_clk));

    flags_wr2rd flags_wr2rd_inst
      (.rd_clk(rd_clk),
       .reset(reset),
       .fifo_full(fifo_full),
       .fifo_almost_full(fifo_almost_full),
       .fifo_empty(fifo_emtpy),
       .fifo_almost_empty(fifo_almost_empty),
       .full(full),
       .almost_full(almost_full),
       .empty(empty),
       .almost_empty(almost_empty));

       FIFO16 #(
      .ALMOST_FULL_OFFSET(12'h008),     // Sets almost full threshold
      .ALMOST_EMPTY_OFFSET(12'h008),    // Sets the almost empty threshold
      .DATA_WIDTH(9),                   // Sets data width to 4, 9, 18, or 36
      .FIRST_WORD_FALL_THROUGH("TRUE") // Sets the FIFO FWFT to "TRUE" or "FALSE" 
   ) FIFO16_2kx9_inst (
      .ALMOSTEMPTY(fifo_almost_empty),       // 1-bit almost empty output flag
      .ALMOSTFULL(fifo_almost_full),         // 1-bit almost full output flag
      .DO({unconnected[23:0], rd_data}),    // 8-bit data output
      .DOP(unconnected[26:25]), // 1-bit parity data output
      .EMPTY(fifo_empty),          // 1-bit empty output flag
      .FULL(fifo_full),            // 1-bit full output flag
      .RDCOUNT(rd_addr),      // 12-bit read count output
      .RDERR(rd_err),          // 1-bit read error output
      .WRCOUNT(wr_addr),      // 12-bit write count output
      .WRERR(wr_err),          // 1-bit write error
      .DI({24'h000000, wr_data}),  // 8-bit data input (rest tied to ground)
      .DIP(4'b0000),    // 1-bit partity input (rest tied to ground)
      .RDCLK(rd_clk),          // 1-bit read clock input
      .RDEN(rd),            // 1-bit read enable input
      .RST(reset),              // 1-bit reset input
      .WRCLK(clk_bufr),          // 1-bit write clock input
      .WREN(wr)             // 1-bit write enable input
   ); 

endmodule // ch_fifo