pn_lock_wr2rd.v

来自「如何使用ISE和FPGA使用指南」· Verilog 代码 · 共 25 行

module pn_lock_wr2rd (input rd_clk,
		      input reset,
		      input pn_lock,
		      output reg pn_lock_rd_clk);
    reg 		     pn_lock_rd_clk_p0;

    //_____________________________________________________________________________________
    // Cross clock domains for pn_lock from wr_clk to rd_clk
    //_____________________________________________________________________________________
    always @ (posedge rd_clk)
    begin
	if (reset)
	begin
	    pn_lock_rd_clk_p0 <= 0;
	    pn_lock_rd_clk <= 0;
	end
	else
	begin
	    pn_lock_rd_clk_p0 <= pn_lock;
	    pn_lock_rd_clk <= pn_lock_rd_clk_p0;
	end // else: !if(reset)
    end // always @ (posedge rd_clk)
endmodule // pn_lock_wr2rd