pn_correlation.v

如何使用ISE和FPGA使用指南

module pn_correlation (input clk_bufio,
		       input clk_bufr_div8,
		       input clk_bufr,
		       input reset,
		       input pn_acq,
		       input data_ch, 
		       output reg pn_fnd, 
		       output [7:0] wr_data);
    parameter [7:0] K = 8'b10001101;

    wire [7:0] 	 sr_data;
    reg [7:0] result;
    integer    j;
    wire       shift1, shift2;

    // Instantiate ISERDES MASTER (5:0)
    ISERDES iserdes_master
      (.O(),
       .Q1(sr_data[0]),
       .Q2(sr_data[1]),
       .Q3(sr_data[2]),
       .Q4(sr_data[3]),
       .Q5(sr_data[4]),
       .Q6(sr_data[5]),
       .SHIFTOUT1(shift1),
       .SHIFTOUT2(shift2),
       .BITSLIP(1'b0),
       .CE1(1'b1),
       .CE2(1'b1),
       .CLK(clk_bufio),
       .CLKDIV(clk_bufr_div8),
       .D(data_ch),
       .DLYCE(1'b0),
       .DLYINC(1'b0),
       .DLYRST(1'b0),
       .OCLK(1'b0),
       .REV(1'b0),
       .SHIFTIN1(1'b0),
       .SHIFTIN2(1'b0),
       .SR(reset));
   defparam iserdes_master.BITSLIP_ENABLE = "FALSE"; // TRUE/FALSE to enable bitslip controller
   defparam iserdes_master.DATA_RATE = "SDR"; // Specify data rate of "DDR" or "SDR" 
   defparam iserdes_master.DATA_WIDTH = 8; // Specify data width - For DDR 4,6,8, or 10
                                         //    For SDR 2,3,4,5,6,7, or 8 
   defparam iserdes_master.INIT_Q1 = 1'b0; // INIT for Q1 register - 1'b1 or 1'b0
   defparam iserdes_master.INIT_Q2 = 1'b0; // INIT for Q2 register - 1'b1 or 1'b0
   defparam iserdes_master.INIT_Q3 = 1'b0; // INIT for Q3 register - 1'b1 or 1'b0
   defparam iserdes_master.INIT_Q4 = 1'b0; // INIT for Q4 register - 1'b1 or 1'b0
   defparam iserdes_master.INTERFACE_TYPE = "NETWORKING"; // Use model - "MEMORY" or "NETWORKING" 
   defparam iserdes_master.IOBDELAY = "NONE"; // Specify outputs where delay chain will be applied
                                            //    "NONE", "IBUF", "IFD", or "BOTH" 
   defparam iserdes_master.IOBDELAY_TYPE = "DEFAULT"; // Set tap delay "DEFAULT", "FIXED", or "VARIABLE" 
   defparam iserdes_master.IOBDELAY_VALUE = 0; // Set initial tap delay to an integer from 0 to 63
   defparam iserdes_master.NUM_CE = 2; // Define number or clock enables to an integer of 1 or 2
   defparam iserdes_master.SERDES_MODE = "MASTER"; // Set SERDES mode to "MASTER" or "SLAVE" 
   defparam iserdes_master.SRVAL_Q1 = 1'b0; // Define Q1 output value upon SR assertion - 1'b1 or 1'b0
   defparam iserdes_master.SRVAL_Q2 = 1'b0; // Define Q2 output value upon SR assertion - 1'b1 or 1'b0
   defparam iserdes_master.SRVAL_Q3 = 1'b0; // Define Q3 output value upon SR assertion - 1'b1 or 1'b0
   defparam iserdes_master.SRVAL_Q4 = 1'b0; // Define Q4 output value upon SR assertion - 1'b1 or 1'b0

    // Instantiate ISERDES SLAVE (7:6)
    ISERDES iserdes_slave
      (.O(),
       .Q1(),
       .Q2(),
       .Q3(sr_data[6]),
       .Q4(sr_data[7]),
       .Q5(),
       .Q6(),
       .SHIFTOUT1(),
       .SHIFTOUT2(),
       .BITSLIP(1'b0),
       .CE1(1'b1),
       .CE2(1'b1),
       .CLK(clk_bufio),
       .CLKDIV(clk_bufr_div8),
       .D(1'b0),
       .DLYCE(1'b0),
       .DLYINC(1'b0),
       .DLYRST(1'b0),
       .OCLK(1'b0),
       .REV(1'b0),
       .SHIFTIN1(shift1),
       .SHIFTIN2(shift2),
       .SR(reset));
   defparam iserdes_slave.BITSLIP_ENABLE = "FALSE"; // TRUE/FALSE to enable bitslip controller
   defparam iserdes_slave.DATA_RATE = "SDR"; // Specify data rate of "DDR" or "SDR" 
   defparam iserdes_slave.DATA_WIDTH = 8; // Specify data width - For DDR 4,6,8, or 10
                                         //    For SDR 2,3,4,5,6,7, or 8 
   defparam iserdes_slave.INIT_Q1 = 1'b0; // INIT for Q1 register - 1'b1 or 1'b0
   defparam iserdes_slave.INIT_Q2 = 1'b0; // INIT for Q2 register - 1'b1 or 1'b0
   defparam iserdes_slave.INIT_Q3 = 1'b0; // INIT for Q3 register - 1'b1 or 1'b0
   defparam iserdes_slave.INIT_Q4 = 1'b0; // INIT for Q4 register - 1'b1 or 1'b0
   defparam iserdes_slave.INTERFACE_TYPE = "NETWORKING"; // Use model - "MEMORY" or "NETWORKING" 
   defparam iserdes_slave.IOBDELAY = "NONE"; // Specify outputs where delay chain will be applied
                                            //    "NONE", "IBUF", "IFD", or "BOTH" 
   defparam iserdes_slave.IOBDELAY_TYPE = "DEFAULT"; // Set tap delay "DEFAULT", "FIXED", or "VARIABLE" 
   defparam iserdes_slave.IOBDELAY_VALUE = 0; // Set initial tap delay to an integer from 0 to 63
   defparam iserdes_slave.NUM_CE = 2; // Define number or clock enables to an integer of 1 or 2
   defparam iserdes_slave.SERDES_MODE = "SLAVE"; // Set SERDES mode to "MASTER" or "SLAVE" 
   defparam iserdes_slave.SRVAL_Q1 = 1'b0; // Define Q1 output value upon SR assertion - 1'b1 or 1'b0
   defparam iserdes_slave.SRVAL_Q2 = 1'b0; // Define Q2 output value upon SR assertion - 1'b1 or 1'b0
   defparam iserdes_slave.SRVAL_Q3 = 1'b0; // Define Q3 output value upon SR assertion - 1'b1 or 1'b0
   defparam iserdes_slave.SRVAL_Q4 = 1'b0; // Define Q4 output value upon SR assertion - 1'b1 or 1'b0

    assign 	    wr_data = sr_data;
    
    // pn_rake
    always @ (posedge clk_bufr)
    begin: pn_rake
	if (reset)
	  pn_fnd <= 0;
	else
	begin
	    if (pn_acq)
	    begin
		for (j = 0; j <= 7; j = j + 1)
		  if (K[j])
		    result[j] = K[j] & sr_data[j];
		  else
		    result[j] = ~K[j] & ~sr_data[j];
		
		//correlation = &result;

		if (&result)
		  pn_fnd <= 1;
		else
		  pn_fnd <= 0;
	    end // if (pn_acq)
	end // else: !if(reset)
    end // block: pn_rake

endmodule // pn_correlation