flags_wr2rd.v

来自「如何使用ISE和FPGA使用指南」· Verilog 代码 · 共 48 行

module flags_wr2rd(input rd_clk,
		   input reset,
		   input fifo_full,
		   input fifo_almost_full,
		   input fifo_empty,
		   input fifo_almost_empty,
		   output reg full,
		   output reg almost_full,
		   output reg empty,
		   output reg almost_empty);
    reg 		  full_p0, almost_full_p0, empty_p0, almost_empty_p0;

    always @ (posedge rd_clk)
    begin
	if (reset)
	begin
	    full_p0 <= 0;
	    almost_full_p0 <= 0;
	    empty_p0 <= 0;
	    almost_empty_p0 <= 0;
	    full <= 0;
	    almost_full <= 0;
	    empty <= 0;
	    almost_empty <= 0;
	end
	else
	begin 
                full_p0         <= fifo_full;          // Metastable reg
                almost_full_p0  <= fifo_almost_full;   // Metastable reg
                empty_p0        <= fifo_empty;         // balance reg
                almost_empty_p0 <= fifo_almost_empty;  // balance reg
                full            <= full_p0;            // cross reg
                almost_full     <= almost_full_p0;     // cross reg
                empty           <= empty_p0;           // balance reg
                almost_empty    <= almost_empty_p0;    // balance reg
//                 full <= fifo_full;
//                 almost_full <= fifo_almost_full;
//                 empty <= fifo_empty;
//                 almost_empty <= fifo_almost_empty;
	end // else: !if(reset)
    end // always @ (posedge rd_clk)
endmodule // flags_wr2rd