correlate_and_accumulate.v

如何使用ISE和FPGA使用指南

module correlate_and_accumulate (input wr_clk_cha, 
				 input wr_clk_chb, 
				 input wr_clk_chc, 
				 input wr_clk_chd, 
				 input rd_clk, 
				 input reset, 
				 input data_cha, 
				 input data_chb, 
				 input data_chc, 
				 input data_chd, 
				 output [7:0] final_data, 
				 output [3:0] valid_ch, 
				 output [20:0] mac_cha, 
				 output [20:0] mac_chb, 
				 output [20:0] mac_chc,
				 output [20:0] mac_chd, 
				 output [3:0] mac_dv);

    wire [7:0] 	  rd_data_cha, rd_data_chb, rd_data_chc, rd_data_chd;
    wire [3:0] 	  rd, pn_lock_rd_clk, almost_full, almost_empty, full, empty;
    wire 	  rd_clk_bufg;
    wire 	 wr_clk_cha_bufio, wr_clk_chb_bufio, wr_clk_chc_bufio, wr_clk_chd_bufio;
    wire 	 wr_clk_cha_bufr, wr_clk_chb_bufr, wr_clk_chc_bufr, wr_clk_chd_bufr;
    wire 	 wr_clk_cha_bufr_div8, wr_clk_chb_bufr_div8, wr_clk_chc_bufr_div8, wr_clk_chd_bufr_div8;

    defparam 	 cha_fifo_inst.pn_correlator_inst.pn_correlation_inst.K = 8'b10001101;
    defparam 	 chb_fifo_inst.pn_correlator_inst.pn_correlation_inst.K = 8'b11100101;
    defparam 	 chc_fifo_inst.pn_correlator_inst.pn_correlation_inst.K = 8'b00101110; 
    defparam 	 chd_fifo_inst.pn_correlator_inst.pn_correlation_inst.K = 8'b11010001;
    
    data_control data_control_inst
      (.clk(rd_clk_bufg), 
       .reset(reset), 
       .pn_lock_rd_clk(pn_lock_rd_clk), 
       .rd_data_cha(rd_data_cha), 
       .rd_data_chb(rd_data_chb), 
       .rd_data_chc(rd_data_chc), 
       .rd_data_chd(rd_data_chd), 
       .rd(rd), 
       .final_data(final_data), 
       .almost_full(almost_full),
       .almost_empty(almost_empty),
       .full(full),
       .empty(empty),
       .valid_ch(valid_ch), 
       .mac_cha(mac_cha), 
       .mac_chb(mac_chb), 
       .mac_chc(mac_chc), 
       .mac_chd(mac_chd), 
       .mac_dv(mac_dv));

    ch_fifo cha_fifo_inst 
      (.rd_clk(rd_clk_bufg),
       .clk_bufio(wr_clk_cha_bufio),
       .clk_bufr(wr_clk_cha_bufr),
       .clk_bufr_div8(wr_clk_cha_bufr_div8),
       .reset(reset), 
       .data_ch(data_cha), 
       .rd_data(rd_data_cha), 
       .rd(rd[0]), 
       .pn_lock_rd_clk(pn_lock_rd_clk[0]), 
       .almost_full(almost_full[0]), 
       .almost_empty(almost_empty[0]),
       .full(full[0]),
       .empty(empty[0]));    

    ch_fifo chb_fifo_inst 
      (.rd_clk(rd_clk_bufg), 
       .clk_bufio(wr_clk_chb_bufio),
       .clk_bufr(wr_clk_chb_bufr),
       .clk_bufr_div8(wr_clk_chb_bufr_div8),
       .reset(reset), 
       .data_ch(data_chb), 
       .rd_data(rd_data_chb), 
       .rd(rd[1]), 
       .pn_lock_rd_clk(pn_lock_rd_clk[1]), 
       .almost_full(almost_full[1]), 
       .almost_empty(almost_empty[1]),
       .full(full[1]),
       .empty(empty[1]));    

    ch_fifo chc_fifo_inst
      (.rd_clk(rd_clk_bufg), 
       .clk_bufio(wr_clk_chc_bufio),
       .clk_bufr(wr_clk_chc_bufr),
       .clk_bufr_div8(wr_clk_chc_bufr_div8),
       .reset(reset), 
       .data_ch(data_chc), 
       .rd_data(rd_data_chc), 
       .rd(rd[2]), 
       .pn_lock_rd_clk(pn_lock_rd_clk[2]), 
       .almost_full(almost_full[2]), 
       .almost_empty(almost_empty[2]),
       .full(full[2]),
       .empty(empty[2]));    

    ch_fifo chd_fifo_inst 
      (.rd_clk(rd_clk_bufg), 
       .clk_bufio(wr_clk_chd_bufio),
       .clk_bufr(wr_clk_chd_bufr),
       .clk_bufr_div8(wr_clk_chd_bufr_div8),
       .reset(reset), 
       .data_ch(data_chd), 
       .rd_data(rd_data_chd), 
       .rd(rd[3]), 
       .pn_lock_rd_clk(pn_lock_rd_clk[3]), 
       .almost_full(almost_full[3]), 
       .almost_empty(almost_empty[3]),
       .full(full[3]),
       .empty(empty[3]));    
    	 			  
	wr_clk_core wr_clk_cha_core (
    .wr_clk(wr_clk_cha), 
    .reset(reset), 
    .wr_clk_bufio(wr_clk_cha_bufio), 
    .wr_clk_bufr(wr_clk_cha_bufr), 
    .wr_clk_bufr_div8(wr_clk_cha_bufr_div8));
	 
	wr_clk_core wr_clk_chb_core (
    .wr_clk(wr_clk_chb), 
    .reset(reset), 
    .wr_clk_bufio(wr_clk_chb_bufio), 
    .wr_clk_bufr(wr_clk_chb_bufr), 
    .wr_clk_bufr_div8(wr_clk_chb_bufr_div8));

	wr_clk_core wr_clk_chc_core (
    .wr_clk(wr_clk_chc), 
    .reset(reset), 
    .wr_clk_bufio(wr_clk_chc_bufio), 
    .wr_clk_bufr(wr_clk_chc_bufr), 
    .wr_clk_bufr_div8(wr_clk_chc_bufr_div8));
	 
	wr_clk_core wr_clk_chd_core (
    .wr_clk(wr_clk_chd), 
    .reset(reset), 
    .wr_clk_bufio(wr_clk_chd_bufio), 
    .wr_clk_bufr(wr_clk_chd_bufr), 
    .wr_clk_bufr_div8(wr_clk_chd_bufr_div8));
	 
endmodule // correlate_and_accumulate