correlate_and_accumulate_xst.ucf

如何使用ISE和FPGA使用指南

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# Step 1
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NET "rd_clk" TNM_NET = "rd_clk";
TIMESPEC "TS_rd_clk" = PERIOD "rd_clk" 3 ns HIGH 50 %;
NET "wr_clk_cha" TNM_NET = "wr_clk_cha";
TIMESPEC "TS_wr_clk_cha" = PERIOD "wr_clk_cha" 6 ns HIGH 50 %;
NET "wr_clk_chb" TNM_NET = "wr_clk_chb";
TIMESPEC "TS_wr_clk_chb" = PERIOD "wr_clk_chb" 6 ns HIGH 50 %;
NET "wr_clk_chc" TNM_NET = "wr_clk_chc";
TIMESPEC "TS_wr_clk_chc" = PERIOD "wr_clk_chc" 6 ns HIGH 50 %;
NET "wr_clk_chd" TNM_NET = "wr_clk_chd";
TIMESPEC "TS_wr_clk_chd" = PERIOD "wr_clk_chd" 6 ns HIGH 50 %;
OFFSET = IN 3 ns BEFORE "wr_clk_cha";
OFFSET = IN 3 ns BEFORE "wr_clk_chb";
OFFSET = IN 3 ns BEFORE "wr_clk_chc";
OFFSET = IN 3 ns BEFORE "wr_clk_chd";
OFFSET = OUT 3 ns AFTER "rd_clk";
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# Step 2 create multi-cycle paths from mac_ch/data_ch_q0 (ffs) to mac_ch/accumulator (ffs)
# It is obvious that these constraints were not directly written by the Xilinx
# constraints editor.  However, you should be able to write the descriptions
# to search for these names from the XCE using the names below.  If you have
# any problems let me know.  I used the wildcards to keep this file shorter
# and more readable.  I did originally use the XCE to generate the constraints
# and groupings then edited them to use the wildcards.  - Rhett
########################################################################
#INST "data_control_inst/mac_inst/mac_ch?_inst/data_ch_q0*" TNM = "mac_data_ch_q0_grp";
#INST "data_control_inst/mac_inst/mac_ch?_inst/data_sign*" TNM = "mac_data_ch_q0_grp";
INST "data_control_inst/mac_inst/mac_ch?_inst/accumulator*" TNM = "mac_accumulator_grp";
#INST "data_control_inst/mac_inst/mac_ch?_inst/product*" TNM = "mac_accumulator_grp";
# allow 3 of 6 cycles be used to propagate data_ch_q0 to accumulator
#TIMESPEC "ts_mac_data_ch_q0_2_mac_accumulator" = FROM "mac_data_ch_q0_grp" TO "mac_accumulator_grp" "TS_rd_clk" * 3;
# allow other 3 of 6 cycles be used to propagate through product
#TIMESPEC "ts_accumulator2accumulator" = FROM "mac_accumulator_grp" TO "mac_accumulator_grp" "TS_rd_clk" * 3;
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# Step 3 Specify multi-cycle paths from the blockrams to ffs
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TIMESPEC "ts_blockrams2ffs" = FROM "RAMS" TO "FFS" "TS_rd_clk" * 3;
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# Step 4 The outputs are active for 8 rd_clk cycels.  The valid signals
# are active for 4 clock cycles.  Allow two internal clock cycles to 
# propagate these values off chip (multi-cycle path).
########################################################################

INST "final_data*.PAD" TNM = "pad_grp_data";
INST "mac_ch?*.PAD" TNM = "pad_grp_data";
INST "mac_dv*.PAD" TNM = "pad_grp_data";
INST "valid_ch*.PAD" TNM = "pad_grp_data";
TIMEGRP "pad_grp_data" OFFSET = OUT 10 ns AFTER "rd_clk";

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# Step 5 Specify multi-cycle paths for the clock enable signals waiting_cntr_en
# to next_ch_en.
########################################################################
#NET "data_control_inst/data_control_fsm_inst/waiting_cntr_en_3" TNM_NET = "tgrp_waiting_cntr_en";
NET "data_control_inst/waiting_cntr_en" TNM_NET = "tgrp_waiting_cntr_en";
NET "data_control_inst/next_ch_en" TNM_NET = "tgrp_next_ch_en";
TIMESPEC "ts_waiting_cntr_en_grp2next_ch_en_grp" = FROM "tgrp_waiting_cntr_en" TO "tgrp_next_ch_en" "TS_rd_clk" * 5;

########################################################################
# Step 6 Specify multi-cycle paths for all ffs driven by dv_enable signal 
########################################################################
NET "data_control_inst/dv_enable" TNM_NET = "tgrp_dv_enable";
#NET "data_control_inst/mac_inst/mac_cha_inst/dv_enable??" TNM_NET = "tgrp_dv_enable";
TIMESPEC "ts_dv_enable2dv_enable" = FROM "tgrp_dv_enable" TO "tgrp_dv_enable" "TS_rd_clk" * 8;
########################################################################
# Step 7 Specify path specific constraint for failing paths from current state (cs) 
# to accumulator counter (accumulator_cntr)
######################################################################## 
#INST data_control_inst/data_control_fsm_inst/cs(*) TNM = tgrp_cs;
#INST data_control_inst/mac_inst/mac_ch?_inst/*accumulator_cntr(*) TNM = tgrp_dsp48_cntr;
#TIMESPEC ts_cs2dsp48_cntr = FROM tgrp_cs TO tgrp_dsp48_cntr TS_rd_clk * 0.99;

########################################################################
# RPM Constraints Go Here
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########################################################################
# U_SET RPM Constraints Go Here
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# U_SET Specification
#INST ch?_fifo_inst/fifo_status_inst/almost_empty U_SET = set_flags_priority;
#INST ch?_fifo_inst/fifo_status_inst/empty U_SET = set_flags_priority;
#INST ch?_fifo_inst/fifo_status_inst/almost_full U_SET = set_flags_priority;
#INST ch?_fifo_inst/fifo_status_inst/full U_SET = set_flags_priority;
#INST data_control_inst/read_ch_arbiter_inst/priority[?] U_SET = set_flags_priority;
# RLOCs
#INST chd_fifo_inst/fifo_status_inst/full RLOC = X0Y7;
#INST chd_fifo_inst/fifo_status_inst/almost_full RLOC = X0Y7;
#INST chd_fifo_inst/fifo_status_inst/empty RLOC = X0Y6;
#INST chd_fifo_inst/fifo_status_inst/almost_empty RLOC = X0Y6;
##
#INST chc_fifo_inst/fifo_status_inst/full RLOC = X0Y5;
#INST chc_fifo_inst/fifo_status_inst/almost_full RLOC = X0Y5;
#INST chc_fifo_inst/fifo_status_inst/empty RLOC = X0Y4;
#INST chc_fifo_inst/fifo_status_inst/almost_empty RLOC = X0Y4;
##
#INST chb_fifo_inst/fifo_status_inst/full RLOC = X0Y3;
#INST chb_fifo_inst/fifo_status_inst/almost_full RLOC = X0Y3;
#INST chb_fifo_inst/fifo_status_inst/empty RLOC = X0Y2;
#INST chb_fifo_inst/fifo_status_inst/almost_empty RLOC = X0Y2;
##
#INST cha_fifo_inst/fifo_status_inst/full RLOC = X0Y1;
#INST cha_fifo_inst/fifo_status_inst/almost_full RLOC = X0Y1;
#INST cha_fifo_inst/fifo_status_inst/empty RLOC = X0Y0;
#INST cha_fifo_inst/fifo_status_inst/almost_empty RLOC = X0Y0;
##
#INST data_control_inst/read_ch_arbiter_inst/priority[3] RLOC = X3Y3;
#INST data_control_inst/read_ch_arbiter_inst/priority[2] RLOC = X3Y3;
#INST data_control_inst/read_ch_arbiter_inst/priority[1] RLOC = X3Y2;
#INST data_control_inst/read_ch_arbiter_inst/priority[0] RLOC = X3Y2;
##
########################################################################
# H_SET RPM Constraints Go Here
########################################################################
#
#INST chd_fifo_inst/fifo_status_inst/full RLOC = X0Y1;
#INST chd_fifo_inst/fifo_status_inst/almost_full RLOC = X0Y1;
#INST chd_fifo_inst/fifo_status_inst/empty RLOC = X0Y0;
#INST chd_fifo_inst/fifo_status_inst/almost_empty RLOC = X0Y0;
##
#INST chc_fifo_inst/fifo_status_inst/full RLOC = X0Y1;
#INST chc_fifo_inst/fifo_status_inst/almost_full RLOC = X0Y1;
#INST chc_fifo_inst/fifo_status_inst/empty RLOC = X0Y0;
#INST chc_fifo_inst/fifo_status_inst/almost_empty RLOC = X0Y0;
##
#INST chb_fifo_inst/fifo_status_inst/full RLOC = X0Y1;
#INST chb_fifo_inst/fifo_status_inst/almost_full RLOC = X0Y1;
#INST chb_fifo_inst/fifo_status_inst/empty RLOC = X0Y0;
#INST chb_fifo_inst/fifo_status_inst/almost_empty RLOC = X0Y0;
##
#INST cha_fifo_inst/fifo_status_inst/full RLOC = X0Y1;
#INST cha_fifo_inst/fifo_status_inst/almost_full RLOC = X0Y1;
#INST cha_fifo_inst/fifo_status_inst/empty RLOC = X0Y0;
#INST cha_fifo_inst/fifo_status_inst/almost_empty RLOC = X0Y0;
##
#INST data_control_inst/read_ch_arbiter_inst/priority[3] RLOC = X0Y1;
#INST data_control_inst/read_ch_arbiter_inst/priority[2] RLOC = X0Y1;
#INST data_control_inst/read_ch_arbiter_inst/priority[1] RLOC = X0Y0;
#INST data_control_inst/read_ch_arbiter_inst/priority[0] RLOC = X0Y0;
##
## Hierarchical RLOCs
#INST chd_fifo_inst/fifo_status_inst RLOC = X0Y0;
#INST chc_fifo_inst/fifo_status_inst RLOC = X0Y2;
#INST chb_fifo_inst/fifo_status_inst RLOC = X0Y4;
#INST cha_fifo_inst/fifo_status_inst RLOC = X0Y6;
#INST data_control_inst/read_ch_arbiter_inst RLOC = X3Y2;

## Hierarchical RLOCs for top-level, required to fully constrain from the top-down
## UN-COMMENT! if you are using H_SET Constraints
#INST chd_fifo_inst RLOC = X0Y0;
#INST chc_fifo_inst RLOC = X0Y0;
#INST chb_fifo_inst RLOC = X0Y0;
#INST cha_fifo_inst RLOC = X0Y0;
#INST data_control_inst RLOC = X0Y0;

########################################################################
# RPM_GRID RPM Constraints Go Here
########################################################################
#INST chd_fifo_inst/fifo_status_inst/empty RPM_GRID = GRID;
#INST chd_fifo_inst/fifo_status_inst/full RLOC = X0Y1;
#INST chd_fifo_inst/fifo_status_inst/almost_full RLOC = X0Y1;
#INST chd_fifo_inst/fifo_status_inst/empty RLOC = X0Y0;
#INST chd_fifo_inst/fifo_status_inst/almost_empty RLOC = X0Y0;
#
#INST chc_fifo_inst/fifo_status_inst/empty RPM_GRID = GRID;
#INST chc_fifo_inst/fifo_status_inst/full RLOC = X0Y1;
#INST chc_fifo_inst/fifo_status_inst/almost_full RLOC = X0Y1;
#INST chc_fifo_inst/fifo_status_inst/empty RLOC = X0Y0;
#INST chc_fifo_inst/fifo_status_inst/almost_empty RLOC = X0Y0;
#
#INST chb_fifo_inst/fifo_status_inst/empty RPM_GRID = GRID;
#INST chb_fifo_inst/fifo_status_inst/full RLOC = X0Y1;
#INST chb_fifo_inst/fifo_status_inst/almost_full RLOC = X0Y1;